公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1999 | A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit | J. H. Lou; J. B. Kuo; JAMES-B KUO | Low-Voltage CMOS VLSI Circuits | | | |
2016 | A Nonlinear Surface-Field Compact Model for Juinctionless Nanowire MOSFET | C. Hong; L. Yang; Q. Cheng; T. Han; J. B. Kuo; Y. Chen; JAMES-B KUO | Workshop on Microelectronics and Electron Devices (WMED) | | | |
1999 | A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold Technique | S. C. Liu; J. B. Kuo; JAMES-B KUO | IEEE International SOI Conference Proceedings | 0 | 0 | |
2003 | A Novel 0.8V BP-DTMOS Content Addressable Memory Cell Circuit Derived from SOI-DTMOS Techniques | E. Shen; J. B. Kuo; JAMES-B KUO | IEEE Conference on Electron Devices and Solid State Circuits | 4 | 0 | |
2001 | A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques | S. C. Liu; Frank Wu; JAMES-B KUO | IEEE Journal of Solid-State Circuits | 17 | 15 | |
0 | A Novel Low-Voltage Silicon-On-Insulator (SOI) CMOS Complementary Pass-Transistor Logic (CPL) Circuit using Asymmetrical Dynamic Threshold Pass-Transistor (ADTPT) Technique | J. B. Kuo; B. T. Wang; JAMES-B KUO | | | | |
2014 | A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles | Q. Cheng; C. Y. Hong; J. B. Kuo; Y. J. Chen; JAMES-B KUO | IEEE Transactions on Electron Devices | 16 | 17 | |
1993 | Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter | Kuo, J.B.; Sim, J.H.; KuoJB | 1993 International Symposium on VLSI Technology, Systems, and Applications, 1993 | 0 | 0 | |
1993 | Amorphous silicon TFT capacitance model using an effective temperature approach | Chen, S.S.; KuoJB | Electronics Letters | 1 | 0 | |
2015 | An Analytic Surface-Field-Based Quasi-Atomistic Model for Nanowire MOSFETs with Random Dopant Fluctuations | C. Hong; Q Cheng; P. Wang; L. Yang; Y. Chen; JAMES-B KUO | IEEE Transactions on Electron Devices | 5 | 5 | |
1991 | Analogue adaptive neural network circuit | Chiang, M.L.; Lu, T.C.; JAMES-B KUO | Circuits, Devices and Systems, IEE Proceedings G | 4 | 2 | |
2006 | Analysis of Fringing Electric Field Related Capacitance Behavior of Narrow-Channel FD SOI NMOS Devices Using 3D Simulation | C. C. Chen; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO | ICSICT | 0 | 0 | |
2003 | Analysis of Gate Misalignment Effect on the Threshold Voltage of Double-Gate (DG) Ultrathin FD SOI NMOS Devices Using a Compact Model Considering Fringing Electric Field Effect | J. B. Kuo; E. C. Sun; M. T. Lin; JAMES-B KUO | IEEE Electron Devices for Microwave and Optoelectronic Applications | 0 | 0 | |
2003 | Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect | Kuo, J.B.; Sun, E.C.; Lin, M.T.; KuoJB | The 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003. | 0 | 0 | |
2008 | Analysis of STI Mechanical-Stress Induced Effects of Nanometer PD SOI NMOS Devices | JAMES-B KUO | SRC Conference | | | |
2008 | Analysis of STI Mechanical-Stress Induced Effects on 40nm PD SOI NMOS Devices | JAMES-B KUO | IEDMS | | | |
2008 | Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region | I. S. Lin; JAMES-B KUO | Solid-State Electronics | 4 | 3 | |
2015 | Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect | S. K. Hu; JAMES-B KUO | Workshop on Microelectronics and Electron Devices (WMED) | | | |
2006 | Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOINMOS device considering the 3-D fringing capacitances using 3-D simulation | C. C. Chen; J. B. Kuo; K. W. Su,; S. Liu; JAMES-B KUO | IEEE Transactions on Electron Devices | 3 | 2 | |
2006 | Analysis of the Gate–Source/Drain Capacitance
Behavior of a Narrow-Channel FD SOI NMOS
Device Considering the 3-D Fringing
Capacitances Using 3-D Simulation | Chen, Chien-Chung ; Kuo, James B. ; Su, Ke-Wei; Liu, Sally | IEEE Transactions on Electron Devices | | | |