公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2017 | Test Methodology for Dual-rail Asynchronous Circuits | Huang, K.-Y.; Shen, T.-Y.; CHIEN-MO LI | Proceedings - Design Automation Conference | | | |
2019 | Test methodology for PCHB/PCFB Asynchronous Circuits | Shen, T.-Y.; Pai, C.-C.; Chen, T.-C.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - International Test Conference | 1 | 0 | |
2018 | Test pattern compression for probabilistic circuits | Chang, C.-M.; Yang, K.-J.; Li, J.C.-M.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 0 | 0 | |
2013 | Test Pattern Modification for Average IR-drop Reduction | CHIEN-MO LI ; WS Ding; HY Hsieh; CHIEN-MO LI | IEEE Int’l Test Conf. | | | |
2016 | Test Pattern Modification for Average IR-Drop Reduction | Ding, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | | | |
2009 | Test Response Compaction in the Presence of Many Unknowns | CHIEN-MO LI ; Wei-Che Wang; James C.-M. Lim; Yi-Chih Sung; Amy Rao; Laung-Terng Wang; CHIEN-MO LI | VTTW | | | |
2011 | Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan | CHIEN-MO LI ; R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI | International Test Conference | | | |
2001 | Testing for Resistive and Stuck Opens | CHIEN-MO LI ; Li, J. C.M.; Tseng, C.W.; E.J. McCluskey; CHIEN-MO LI | International Test Conference | | | |
2000 | Testing for tunneling opens. | Li, Chien-Mo James; McCluskey, Edward J.; CHIEN-MO LI | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | | | |
2013 | Testing Leakage Faults of Power TSV in 3D IC | CHIEN-MO LI ; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI | IEEE Int’l workshop on 3D IC | | | |
2014 | Testing of TSV-induced small delay faults for 3-D integrated circuits | Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James C.-M. Li; Krishnendu Chakrabarty; YI-CHANG LU ; CHIEN-MO LI | IEEE Trans. Very Large Scale Integration (VLSI) Systems | 17 | 13 | |
2012 | Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits, | CHIEN-MO LI ; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI | IEEE 3D IC Test workshop | | | |
2012 | Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC | CHIEN-MO LI ; C. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI | Active and Passive Electronic Components | | | |
2011 | Thermal-aware Test scheduling for 3D ICs | CHIEN-MO LI ; CY Hsu; JCM Li; K. Chakrbarty; CHIEN-MO LI | IEEE Int’l 3D IC Test Workshop | | | |
2009 | Time-space test response compaction and diagnosis based on BCH codes | CHIEN-MO LI ; F. M. Wang; W.-C. Wang; CHIEN-MO LI | IET Computers & Digital Techniques | | 0 | |
2014 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk | CHIEN-MO LI ; M. H. Tsai; W. S. Ding; H. Y. Hsieh; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | | 3 | |
2012 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk | CHIEN-MO LI ; MH Tsai; WS Ting; CHIEN-MO LI | VTTW | | | |
2012 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk, | CHIEN-MO LI ; M. H. Tsai; W. S. Ting; CHIEN-MO LI | ITC | | | |
2008 | Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture Clocks | CHIEN-MO LI ; Shang-Feng Chao; CHIEN-MO LI | VLSI/CAD | | | |
2009 | Transition Fault Diagnosis Using At-speed Test Patterns | CHIEN-MO LI ; Shang-Feng Chao; Jheng-Yang Ciou; CHIEN-MO LI | IEEE Int’l Workshop on RTL and High Level Testing | | | |