Publications

Results 1-87 of 87 (Search time: 0.007 seconds).

Issue DateTitleAuthor(s)SourcescopusWOSFulltext/Archive link
12019Efficient search of layout hotspot patterns for matching SEM images using multilevel pixelationSean Shang-En Tseng; Wei-Chun Chang; Iris Hui-Ru Jiang; Jun Zhu; James P. Shiely; HUI-RU JIANG ; 江蕙如SPIE Advanced Lithography Conference (AL-2019)00
22019Multiple patterning layout compliance with minimizing topology disturbance and polygon displacementHua-Yu Chang; Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如28th ACM International Symposium on Physical Design (ISPD-2019)00
32019Graceful register clustering by effective mean shift algorithm for power and timing balancingYa-Chu Chang; Tung-Wei Lin; Iris Hui-Ru Jiang; Gi-Joon Nam; HUI-RU JIANG ; 江蕙如28th ACM International Symposium on Physical Design (ISPD-2019)00
42019Novel guiding template and mask assignment for DSA-MP hybrid lithography using multiple BCP materialsYi-Ting Lin; Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如56th ACM/IEEE Design Automation Conference (DAC-2019)00
52019iClaire: A Fast and General Layout Pattern Classification Algorithm with Clip Shifting and Centroid RecreationChang, W.; Jiang, I.H.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems00
62019Graph-based modeling, scheduling, and verification for intersection management of intelligent vehiclesLin, Y.-T.; Hsu, H.; Lin, S.-C.; Lin, C.-W.; Jiang, I.H.-R.; Liu, C.; HUI-RU JIANG ACM Transactions on Embedded Computing Systems10
72018DATC RDF: An academic flow from logic synthesis to detailed routingJinwook Jung; Iris Hui-Ru Jiang; Jianli Chen; Shih-Ting Lin; Yih-Lang Li; Victor N. Kravets; Gi-Joon Nam; HUI-RU JIANG ; 江蕙如IEEE/ACM International Conference on Computer Aided Design (ICCAD-2018)40
82018COSAT: Congestion, obstacle, and slew Aware tree construction for multiple power domain designChien-Pang Lu; Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如55th ACM/EDAC/IEEE Design Automation Conference (DAC-2018)00
92018iTimerM: A compact and accurate timing macro model for efficient hierarchical timing analysisPei-Yu Lee; Iris Hui-Ru Jiang; HUI-RU JIANG accepted by ACM Transactions on Design Automation of Electronic Systems (ACM TODAES)01
102018OWARU: Free space-aware timing-driven incremental placement with critical path smoothingJinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)23
112018Recent research and challenges in multiple patterning layout decompositionJiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI00
122018FastPass: Fast timing path search for generalized timing exception handlingLee, P.-Y.; Jiang, I.H.-R.; Chen, T.-C.; HUI-RU JIANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC00
132018Timing Macro Modeling for Efficient Hierarchical Timing Analysis.Jiang, Iris Hui-Ru; Lee, Pei-Yu; HUI-RU JIANG 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 201800
142017DATC RDF: Robust design flow databaseJinwook Jung; Pe-Yu Lee; Yan-Shiun Wu; Nima Darav; Iris Hui-Ru Jiang; Gi-Joon Nam; Victor N. Kravets; Laleh Behjat; Yih-Lang Li; HUI-RU JIANG ; 江蕙如IEEE/ACM International Conference on Computer Aided Design (ICCAD-2017)
152017iClaire: A fast and general layout pattern classification algorithmWei-Chun Chang; Iris Hui-Ru Jiang; Yen-Ting Yu; Wei-Fang Liu; HUI-RU JIANG ; 江蕙如54th ACM/EDAC/IEEE Design Automation Conference (DAC-2017)100
162017Power and area efficient hold time fixing by free metal segment allocationWei-Lun Chiu; Iris Hui-Ru Jiang; Chien-Pang Lu; Yu-Tung Chang; HUI-RU JIANG ; 江蕙如54th ACM/EDAC/IEEE Design Automation Conference (DAC-2017)00
172017DRC-based hotspot detection considering edge tolerance and incomplete specificationYen-Ting Yu; Hui-Ru Jiang; Yumin Zhang; Charles C. Chiang; HUI-RU JIANG ; 江蕙如
182017iTimerM: Compact and accurate timing macro modeling for hierarchical timing analysisPei-Yu Lee; Iris Hui-Ru Jiang; Ting-You Yang; HUI-RU JIANG ; 江蕙如26th ACM International Symposium on Physical Design (ISPD-2017)
192017Multiple patterning layout decomposition considering complex coloring rules and density balancingIris Hui-Ru Jiang; Hua-Yu Chang; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)44
202017Fast low power rule checking for multiple power domain design.Lu, Chien-Pang; Jiang, Iris Hui-Ru; HUI-RU JIANG Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 201700
212017DATC RDF: Robust design flow database: Invited paperJung, J.; Lee, P.-Y.; Wu, Y.-S.; Darav, N.K.; Jiang, I.H.-R.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; Nam, G.-J.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD40
222017iTimerM: Compact and accurate timing macro modeling for efficient hierarchical timing analysisLee, P.-Y.; Jiang, I.H.-R.; Yang, T.-Y.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design20
232016Analytical clustering score with application to post-placement register clusteringChang Xu; Guojie Luo; Peixin Li; Yiyu Shi; Iris Hui-Ru Jiang; HUI-RU JIANG ACM Transactions on Design Automation of Electronic Systems (ACM TODAES)01
242016OpenDesign flow database: The infrastructure for VLSI design and design automation researchJung, J.; Jiang, I.H.-R.; Nam, G.-J.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD70
252016Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuitsSchlichtmann, U.; Hashimoto, M.; Jiang, I.H.-R.; Li, B.; HUI-RU JIANG Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC00
262016Multiple patterning layout decomposition considering complex coloring rulesChang, H.-Y.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings - Design Automation Conference80
272016Resource-aware functional ECO patch generationCheng, A.-C.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 20167
282016ITimerC 2.0: Fast incremental timing and CPPR analysisLee, P.-Y.; Jiang, I.H.-R.; Li, C.-R.; Chiu, W.-L.; Yang, Y.-M.; HUI-RU JIANG 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 201550
292016OWARU: Free space-aware timing-driven incremental placementJung, J.; Nam, G.-J.; Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD20
302016GasStation: Power and area efficient buffering for multiple power domain designLu, C.-P.; Jiang, I.H.-R.; Hsu, C.-H.; HUI-RU JIANG 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 201500
312015Analytical Clustering score with application to post-placement multi-bit flip-flop mergingXu, C.; Li, P.; Luo, G.; Shi, Y.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design50
322015ITimerC: Common path pessimism removal using effective reduction methodsYang, Y.-M.; Chang, Y.-W.; Jiang, I.H.-R.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD110
332015DRC-based hotspot detection considering edge tolerance and incomplete specificationYu, Y.-T.; Jiang, I.H.-R.; Zhang, Y.; Chiang, C.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD60
342015Machine-learning-based hotspot detection using topological classification and critical feature extractionYu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems4642
352015Criticality-dependency-aware timing characterization and analysisYang, Y.-M.; Tam, K.H.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings - Design Automation Conference120
362015Feature detection for image analytics via FPGA accelerationChang, H.-Y.; Jiang, I.H.-R.; Hofstee, H.P.; Jamsek, D.; Nam, G.-J.; HUI-RU JIANG IBM Journal of Research and Development77
372015Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurationsJiang, I.H.-R.; Nam, G.-J.; Chang, H.-Y.; Nassif, S.R.; Hayes, J.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD60
382014Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilogCheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG ACM Transactions on Design Automation of Electronic Systems11
392014The overview of 2014 CAD contest at ICCAD.Jiang, Iris Hui-Ru; Viswanathan, Natarajan; Chen, Tai-Chen; Li, Jin-Fu; HUI-RU JIANG The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 201400
402014Functional ECO using metal-configurable gate-array spare cellsChang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG Proceedings - Design Automation Conference10
412014PushPull: Short-path padding for timing error resilient circuitsYang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems1210
422013Machine-learning-based hotspot detection using topological classification and critical feature extractionYu, Y.-T.; Lin, G.-H.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG Proceedings - Design Automation Conference350
432013ECO optimization using metal-configurable gate-array spare cellsChang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems22
442013FF-bond: Multi-bit flip-flop bonding at placementTsai, C.-C.; Shi, Y.; Luo, G.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design180
452013The overview of 2013 CAD contest at ICCAD.Jiang, Iris Hui-Ru; Li, Zhuo; Wang, Hwei-Tseng; Viswanathan, Natarajan; HUI-RU JIANG The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 201300
462013PushPull: Short path padding for timing error resilient circuitsYang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design30
472013Pulsed-latch replacement using concurrent time borrowing and clock gatingChang, C.-L.; Jiang, I.H.-R.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems87
482012INTEGRA: Fast multibit flip-flop clustering for clock power savingJiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems3527
492012Novel pulsed-latch replacement based on time borrowing and spiral clusteringChang, C.-L.; Jiang, I.H.-R.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, A.S.-H.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design50
502012ECOS: Stable matching based metal-only ECO synthesisJiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG IEEE Transactions on Very Large Scale Integration (VLSI) Systems67
512012Accurate process-hotspot detection using critical design rule extractionYu, Y.-T.; Chan, Y.-C.; Sinha, S.; Jiang, I.H.-R.; Chiang, C.; HUI-RU JIANG Proceedings - Design Automation Conference490
522012Timing ECO optimization using metal-configurable gate-array spare cellsChang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG Proceedings - Design Automation Conference40
532012Timing ECO optimization via B?zier curve smoothing and fixability identificationChang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems88
542012Reliability-driven power/ground routing for analog ICsLin, J.-W.; Ho, T.-Y.; Jiang, I.H.-R.; HUI-RU JIANG ACM Transactions on Design Automation of Electronic Systems32
552012Opening: Introduction to CAD contest at ICCAD 2012: CAD contest.Jiang, Iris Hui-Ru; Li, Zhuo; Li, Yih-Lang; HUI-RU JIANG 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 201200
562012Generic integer linear programming formulation for 3D IC partitioningLee, W.-Y.; Jiang, I.H.-R.; Mei, T.-W.; HUI-RU JIANG Journal of Information Science and Engineering1
572012WiT: Optimal wiring topology for electromigration avoidanceJiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG IEEE Transactions on Very Large Scale Integration (VLSI) Systems1818
582011INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphsJiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design220
592011Simultaneous functional and timing ECO.Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen; HUI-RU JIANG Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011150
602011Timing ECO optimization via B?zier curve smoothing and fixability identificationChang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD20
6120113DICE: 3D IC cost evaluation based on fast tier number estimationChan, C.-C.; Yu, Y.-T.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011150
622011Recent research development in metal-only ECOTan, C.-Y.; Jiang, I.H.-R.; HUI-RU JIANG Midwest Symposium on Circuits and Systems30
632010Simultaneous voltage island generation and floorplanningLi, H.-Y.; Jiang, I.H.-R.; Chen, H.-M.; HUI-RU JIANG Proceedings - IEEE International SOC Conference, SOCC 201020
642010Optimal wiring topology for electromigration avoidance considering multiple layers and obstaclesJiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG Proceedings of the International Symposium on Physical Design110
652010Analog placement and global routing considering wiring symmetryYang, Y.-M.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010120
662010Live demo: ECOS 1.0: A metal-only ECO synthesizerJiang, I.H.-R.; Chang, H.-Y.; HUI-RU JIANG ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems00
672009POSA: Power-state-aware buffered tree constructionJiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG Proceedings - IEEE International Symposium on Circuits and Systems00
682009Generic integer linear programming formulation for 3D IC partitioningJiang, I.H.-R.; HUI-RU JIANG Proceedings - IEEE International SOC Conference, SOCC 2009240
692009VIFI-CMP: Variability-tolerant chip-multiprocessors for throughput and powerLee, W.Y.; Jiang, I.H.-R.; HUI-RU JIANG Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI10
702009Matching-based minimum-cost spare cell selection for design changes.Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi; HUI-RU JIANG Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009170
712008Power-state-aware buffered tree constructionJiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG 26th IEEE International Conference on Computer Design 2008, ICCD30
722008Unification of obstacle-avoiding rectilinear steiner tree constructionJiang, I.H.-R.; Lin, S.-W.; Yu, Y.-T.; HUI-RU JIANG 2008 IEEE International SOC Conference, SOCC40
732008Topology generation and floorplanning for low power application-specific network-on-chipsLee, W.-Y.; Jiang, I.H.-R.; HUI-RU JIANG 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT30
742008Configurable rectilinear steiner tree construction for SoC and nano technologiesJiang, I.H.R.; Yu, Y.T.; HUI-RU JIANG 26th IEEE International Conference on Computer Design 2008, ICCD10
752007Performance constraints aware voltage Islands generation in SoC floorplan designLu, M.-C.; Wu, M.-C.; Chen, H.-M.; Jiang, H.-R.; HUI-RU JIANG 2006 IEEE International Systems-on-Chip Conference, SOC30
762006Reliable crosstalk-driven interconnect optimizationJiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; HUI-RU JIANG ACM Transactions on Design Automation of Electronic Systems1312
772006Reliable crosstalk-driven interconnect optimization.Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ACM Trans. Design Autom. Electr. Syst.01
782004Simultaneous floorplan and buffer-block optimizationJiang, I.H.-R.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; HUI-RU JIANG IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems102
792003Simultaneous floorplanning and buffer block planning.Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan; HUI-RU JIANG Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 200300
802002Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning.Chang, Nicholas Chia-Yuan; Chang, Yao-Wen; Jiang, Iris Hui-Ru; HUI-RU JIANG 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 200210
812000Optimal reliable crosstalk-driven interconnect optimization.Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 200060
822000Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG IEEE Trans. on CAD of Integrated Circuits and Systems4738
831999Optimum loading dispersion for high-speed tree-type decision circuitry.Jiang, Jie-Hong Roland; Jiang, Iris Hui-Ru; HUI-RU JIANG Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 199900
841999Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation.Jiang, Iris Hui-Ru; Jou, Jing-Yang; Chang, Yao-Wen; HUI-RU JIANG Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999.80
851999Hierarchical Floorplan Design on the Internet.Lin, Jiann-Horng; Jou, Jing-Yang; Jiang, Iris Hui-Ru; HUI-RU JIANG Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 199900
861999A clustering- and probability-based approach for time-multiplexed FPGA partitioning.Chao, Mango Chia-Tso; Wu, Guang-Ming; Jiang, Iris Hui-Ru; Chang, Yao-Wen; HUI-RU JIANG Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 199900
870Please see http://dblp.uni-trier.de/pers/hd/j/Jiang:Iris_Hui=RuIris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如