公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2011 | An at-speed self-testable technique for the high speed domino adder | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | Proceedings of the Custom Integrated Circuits Conference | 1 | 0 | |
2012 | An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example | Wang, Y.-S.; Hsieh, M.-H.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | IEEE Transactions on Circuits and Systems I: Regular Papers | 3 | 3 | |
2019 | ATPG and test compression for probabilistic circuits | Yang, K.-C.; Lee, M.-T.; Wu, C.-H.; CHIEN-MO LI | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 | | | |
2020 | Automatic IR-Drop ECO Using Machine Learning | Lin H.-Y; Fang Y.-C; Liu S.-T; Chen J.-X; Li C.-M; Fang E.J.-W.; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | | | |
2022 | Automatic test configuration and pattern generation (ATCPG) for neuromorphic chips | Chiu, I. Wei; Chen, Xin Ping; Hu, Jennifer Shueh Inn; CHIEN-MO LI | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
2017 | Automatic test pattern generation | Cheng, K.-T.T.; Wang, L.-C.; Li, H.; CHIEN-MO LI | Electronic Design Automation for IC System Design, Verification, and Testing | | | |
2013 | Automatic test pattern generation for delay defects using timed characteristic functions. | Ho, Shin-Yann; Lin, Shuo-Ren; Yuan, Ko-Lung; Kuo, Chien-Yen; Liao, Kuan-Yu; Jiang, Jie-Hong R.; CHIEN-MO LI ; JIE-HONG JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | 2 | 0 | |
2013 | Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM | CHIEN-MO LI ; BC Bai; C-L Hsu; MH Wu; CA Chen; YW Chen; KL Luo; LC Cheng; CHIEN-MO LI | IEEE Asian Test Symposium | | | |
2009 | BIST design optimization for large-scale embedded memory cores. | Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 7 | 0 | |
2009 | Bridging Fault Diagnosis to Identify the Layer of Systematic Defects | CHIEN-MO LI ; B. R. Chen; CHIEN-MO LI | Asian Test Symposium | | | |
2008 | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise, | CHIEN-MO LI ; Hsiu-Ting Lin; Jen-Yang Wen; James Li; Ming-Tung Chang; Min-Hsiu Tsai; Sheng-Chih Huang; Chih-Mou Tseng; CHIEN-MO LI | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise | | | |
2021 | Chip Performance Prediction Using Machine Learning Techniques | Su M.-Y; Lin W.-C; Kuo Y.-T; Li C.-M; Fang E.J.-W; Hsueh S.S.-Y.; CHIEN-MO LI | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | | | |
2021 | Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits | Chen T.-C; Pai C.-C; Hsieh Y.-Z; Tseng H.-Y; Chien-Mo J; Liu T.-T; CHIEN-MO LI ; TSUNG-TE LIU ; Chiu I.-W | Journal of Electronic Testing: Theory and Applications (JETTA) | 0 | 0 | |
2005 | Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains | CHIEN-MO LI ; H.M. Lin; CHIEN-MO LI | International Test Conference | | | |
2007 | Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis | CHIEN-MO LI ; J. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI | IEEE Transactions on Computers | | | |
2013 | Compact Test Pattern Selection for Small Delay Defect | CHIEN-MO LI ; J. Y. Chang; K. Y. Liao; S. C. Hsu; J. C. M. Li; J. C. Rau; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 18 | |
2011 | Compact test pattern Selection for Small Delay Defects | CHIEN-MO LI ; CY Chang; K.Y, Liao; CHIEN-MO LI | VLSI/CAD | | | |
2006 | CRC BIST: A Low Peak Power Self Technique | CHIEN-MO LI ; Bo-Hua Chen; CHIEN-MO LI | VLSI/CAD | | | |
2010 | CSER: BISER-based concurrent soft-error resilience | CHIEN-MO LI ; JIUN-LANG HUANG ; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | | | |
2007 | Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies | CHIEN-MO LI ; C.Y. Lee; H.M. Lin; F.M. Wang; CHIEN-MO LI | IEEE Asian South Pacific Design Automation Conference (ASP-DAC) | | | |