公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2006 | Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Gate Tunneling Leakage Current | JAMES-B KUO | MIEL | | | |
2011 | Cell-based leakage power reduction priority (CBLPRP) optimization methodology for designing SOC applications using MTCMOS technique | S. F. Huang; R. S. Shen; J. B. Kuo; JAMES-B KUO | Power and Timing Modeling Optimization Symposium | 2 | 0 | |
2005 | CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects | Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO | HKEDSSC | 0 | 0 | |
2010 | Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp | C. F. Yen; J. B. Kuo; JAMES-B KUO | IEDMS | | | |
2002 | Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion | S. C. Lin; J. B. Kuo; JAMES-B KUO | IEEE Transactions on Electron Devices | 3 | 1 | |
2000 | A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation | Lin S.-C; JAMES-B KUO ; Huang K.-T; Sun S.-W. | IEEE Transactions on Electron Devices | 23 | 16 | |
2002 | Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously | S. C. Lin; JAMES-B KUO | IEEE Transactions on Electron Devices | 1 | 1 | |
2009 | Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide | C. H. Lin; J. B. Kuo; JAMES-B KUO | Solid State Electronics | 1 | 1 | |
1994 | Closed-form physical drain current model considering energy balance equation and source resistance for deep submicron n-channel metal-oxide-semiconductor devices | Ma Shyh-Yih; JAMES-B KUO | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 1 | | |
1994 | A closed-form physical drain current model considering energy balance equation and source resistance for deep submicron n-channel metal-oxide-semiconductor devices | Ma S.-Y; JAMES-B KUO | Japanese Journal of Applied Physics | 0 | 1 | |
1994 | Closed-form physical model for VLSI bipolar devices considering energy transport | Huang, H.J.; Lu, T.C.; KuoJB | Electronics Letters | 2 | 1 | |
2004 | CMOS Digital IC | JAMES-B KUO | | | | |
1998 | CMOS VLSI Engineering: Silicon-on-Insulator (SOI) | J. B. Kuo; K. W. Su; JAMES-B KUO | | | | |
1992 | A Coded Block Adaptive Network System with a Radical-Partitioned Structure for Large-Volume Chinese Characters Recognition | 郭正邦 ; Mao, Mark. W.; Kao, James B. | Neural Networks | | | |
1991 | A coded block adaptive neural network structure for pattern recognition VLSI | Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB | 1991 International Symposium on VLSI Technology, Systems, and Applications | 2 | 0 | |
2002 | Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation | J. B. Kuo; S. C. Lin; JAMES-B KUO | IEDMS | | | |
1997 | Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects | Kuo, J.B.; Su, K.W.; KuoJB | IEEE International SOI Conference | 0 | 0 | |
2006 | Compact Gate Tunneling Current Model Considering Distributed Effect for Sub-100nm NMOS Devices with Ultra-thin (1nm) Gate Oxide | C. H. Lin; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO | IEDMS | | | |
2002 | Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation | J. B. Kuo; S. C. Lin; JAMES-B KUO | IEDMS | | | |
2009 | Compact Modelign of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation | JAMES-B KUO | NSC Seminar | | | |