第 1 到 159 筆結果,共 159 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2023 | Quantized Neural Network Synthesis for Direct Logic Circuit Implementation | Huang, Yu Shan; JIE-HONG JIANG ; Mishchenko, Alan | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
2 | 2022 | Design and Automation for Quantum Computation and Quantum Technologies | JIE-HONG JIANG ; De Micheli, Giovanni; Smith, Kaitlin; Soeken, Mathias | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 0 | 0 | |
3 | 2022 | Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective | De Micheli, Giovanni; JIE-HONG JIANG ; Rand, Robert; Smith, Kaitlin; Soeken, Mathias | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 4 | 2 | |
4 | 2022 | Quantifier Elimination in Stochastic Boolean Satisfiability | Wang, Hao Ren; Tu, Kuan Hua; JIE-HONG JIANG ; Scholl, Christoph | Leibniz International Proceedings in Informatics, LIPIcs | 1 | 0 | |
5 | 2022 | Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification | Wei, Chun Yu; Tsai, Yuan Hung; Jhang, Chiao Shan; JIE-HONG JIANG | Proceedings - Design Automation Conference | 6 | 0 | |
6 | 2022 | Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability | Hsieh, Cheng Han; JIE-HONG JIANG | IJCAI International Joint Conference on Artificial Intelligence | 1 | ||
7 | 2022 | Reconfigurable Biochemical Circuit Synthesis from Biomachine Specification | Wang, Chang Jun; JIE-HONG JIANG | BioCAS 2022 - IEEE Biomedical Circuits and Systems Conference: Intelligent Biomedical Systems for a Better Future, Proceedings | 0 | 0 | |
8 | 2022 | Partial Equivalence Checking of Quantum Circuits | Chen, Tian Fu; JIE-HONG JIANG ; Hsieh, Min Hsiu | Proceedings - 2022 IEEE International Conference on Quantum Computing and Engineering, QCE 2022 | 3 | 0 | |
9 | 2021 | A Circuit-Based SAT Solver for Logic Synthesis | Zhang H.-T; JIE-HONG JIANG ; Mishchenko A. | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 6 | 0 | |
10 | 2021 | Compatible Equivalence Checking of X-Valued Circuits | Wang Y.-N; Luo Y.-R; Chien P.-C; Wang P.-L; Wang H.-R; Lin W.-H; JIE-HONG JIANG ; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
11 | 2021 | Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty | Lee N.-Z; JIE-HONG JIANG | 35th AAAI Conference on Artificial Intelligence, AAAI 2021 | 5 | ||
12 | 2021 | A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving | Chen P.-W; Huang Y.-C; JIE-HONG JIANG | 35th AAAI Conference on Artificial Intelligence, AAAI 2021 | 8 | ||
13 | 2021 | Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization | JIE-HONG JIANG | Proceedings -Design, Automation and Test in Europe, DATE | |||
14 | 2021 | Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation | Chi C; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
15 | 2021 | Constraint Solving for Synthesis and Verification of Threshold Logic Circuits | Lee N.-Z; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
16 | 2021 | Deep Integration of Circuit Simulator and SAT Solver | Zhang H.-T; Jiang J.-H.R; Amaru L; Mishchenko A; Brayton R.; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
17 | 2021 | SAT-Based On-Track Bus Routing | Zhang H.-T; Fujita M; Cheng C.-K; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
18 | 2021 | Homing Sequence Derivation with Quantified Boolean Satisfiability | Tu K; Wang H; Jiang J.R; Kushik N; Yevtushenko N.; JIE-HONG JIANG | IEEE Transactions on Computers | |||
19 | 2021 | Bit-Slicing the Hilbert Space: Scaling up Accurate Quantum Circuit Simulation | Tsai Y.-H; Jiang J.-H.R; Jhang C.-S.; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
20 | 2020 | Engineering Change Order for Combinational and Sequential Design Rectification | Jiang, J.-H.R.; Kravets, V.N.; Lee, N.-Z.; JIE-HONG JIANG | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 | |||
21 | 2020 | Learning to Automate the Design Updates from Observed Engineering Changes in the Chip Development Cycle | Kravets, V.N.; Jiang, J.-H.R.; Riener, H.; JIE-HONG JIANG | Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 | |||
22 | 2020 | SFO: A scalable approach to fanout-bounded logic synthesis for emerging technologies | Zhang H.-T; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
23 | 2020 | Symbolic gas vulnerability detection and attack synthesis | Peng M.H; Yu F; JIE-HONG JIANG | Proceedings of the 24th Pacific Asia Conference on Information Systems: Information Systems (IS) for the Future, PACIS 2020 | |||
24 | 2020 | Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning | Lin Y.-C; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
25 | 2020 | Symbolic gas vulnerability detection and attack synthesis | Peng M.H; Yu F; JIE-HONG JIANG | Proceedings of the 24th Pacific Asia Conference on Information Systems: Information Systems (IS) for the Future, PACIS 2020 | |||
26 | 2020 | Time multiplexing via circuit folding | Chien P.-C; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
27 | 2020 | Symbolic Uniform Sampling with XOR Circuits | Lin Y.-T; Jiang J.-H.R; Kravets V.N.; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
28 | 2020 | Circuit learning for logic regression on high dimensional boolean space | Chen P.-W; Huang Y.-C; Lee C.-L; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
29 | 2019 | A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving | Christoph Scholl; Jie-Hong R. Jiang; Ralf Wimmer; Aile Ge-Ernst; JIE-HONG JIANG | AAAI Conference on Artificial Intelligence (AAAI) | |||
30 | 2019 | An approximation algorithm to the optimal switch control of reconfigurable battery packs | Shih-Yu Chen; Jie-Hong R. Jiang; Shou-Hung Welkin Ling; Shih-Hao Liang; Mao-Cheng Huang; JIE-HONG JIANG ; 江介宏 | Asia and South Pacific Design Automation Conference (ASP-DAC) | 0 | 0 | |
31 | 2019 | A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving | Christoph Scholl; Jie-Hong R. Jiang; Ralf Wimmer; Aile Ge-Ernst; JIE-HONG JIANG ; 江介宏 | AAAI Conference on Artificial Intelligence (AAAI) | |||
32 | 2019 | Disjoint-support decomposition and extraction for interconnect-driven threshold logic synthesis | Chen, H.; Hung, S.-C.; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
33 | 2019 | A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving. | Scholl, Christoph; Jiang, Jie-Hong Roland; Wimmer, Ralf; Ge-Ernst, Aile; JIE-HONG JIANG | The Thirty-Third AAAI Conference on Artificial Intelligence, AAAI 2019, The Thirty-First Innovative Applications of Artificial Intelligence Conference, IAAI 2019, The Ninth AAAI Symposium on Educational Advances in Artificial Intelligence, EAAI 2019, Honolulu, Hawaii, USA, January 27 - February 1, 2019. | |||
34 | 2019 | A Cube Distribution Approach to QBF Solving and Certificate Minimization. | Chen, Li-Cheng; JIE-HONG JIANG | Principles and Practice of Constraint Programming - 25th International Conference, CP 2019, Stamford, CT, USA, September 30 - October 4, 2019, Proceedings | |||
35 | 2019 | Comprehensive search for ECO rectification using symbolic sampling | Kravets, V.N.; Lee, N.-Z.; Jiang, J.-H.R.; JIE-HONG JIANG | Proceedings - Design Automation Conference | |||
36 | 2019 | Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. | Chang, Yi-Fan Evan; Huang, Ruei-Yang; JIE-HONG JIANG | 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019 | |||
37 | 2019 | Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits. | Lin, Zi-Jun; Huang, Wei-Chih; JIE-HONG JIANG | 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), Fredericton, NB, Canada, May 21-23, 2019 | |||
38 | 2019 | Searching parallel separating hyperplanes for effective compression of threshold logic networks | Lee, S.-Y.; Lee, N.-Z.; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
39 | 2019 | Biochemical Threshold Function Implementation with Zero-Order Ultrasensitivity | Huang, W.-C.; Jiang, J.-H.R.; Fages, F.; Molina, F.; JIE-HONG JIANG | BioCAS 2019 - Biomedical Circuits and Systems Conference, Proceedings | |||
40 | 2019 | Time-frame folding: Back to the sequentiality | Chien, P.-C.; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
41 | 2018 | Efficient Computation of ECO Patch Functions | A. Q. Dao; N.-Z. Lee; L.-C. Chen; P.-H. Lin; J.-H. R. Jiang; A. Mishchenko; R. K. Brayton; JIE-HONG JIANG ; 江介宏 | Design Automation Conference (DAC) | 14 | 0 | |
42 | 2018 | Cost-Aware Patch Generation for Multi-Target Function Rectification of Engineering Change Orders | H.-T. Zhang; J.-H. R. Jiang; JIE-HONG JIANG ; 江介宏 | Design Automation Conference (DAC) | 7 | 0 | |
43 | 2018 | Towards Formal Evaluation and Verification of Probabilistic Design | Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | IEEE Transactions on Computers | 9 | 7 | |
44 | 2018 | Static Detection of API Call Vulnerabilities in iOS Executables | C.-H. Lin; F. Yu; J.-H. R. Jiang; T. Bultan; JIE-HONG JIANG ; 江介宏 | International Conference on Software Engineering (ICSE) | 0 | 0 | |
45 | 2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
46 | 2018 | Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation | C.-C. Chi; J.-H. R. Jiang; JIE-HONG JIANG ; 江介宏 | 37th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 | 17 | 0 | |
47 | 2018 | Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection | N.-Z. Lee; Y.-S. Wang; J.-H. R. Jiang; JIE-HONG JIANG ; 江介宏 | International Joint Conference on Artificial Intelligence (IJCAI) | 7 | 0 | |
48 | 2018 | A Symbolic Model Checking Approach to the Analysis of String and Length Constraints | H.-E. Wang; S.-Y. Chen; F. Yu; J.-H. R. Jiang; JIE-HONG JIANG ; 江介宏 | International Conference on Automated Software Engineering (ASE) | 9 | 0 | |
49 | 2018 | Canonicalization of Threshold Logic Representation and its Applications | S.-Y. Lee; N.-Z. Lee; J.-H. R. Jiang; JIE-HONG JIANG ; 江介宏 | Int’l Conf. on Computer-Aided Design (ICCAD) | 9 | 0 | |
50 | 2018 | Recombinase-based genetic circuit optimization | Lai, C.-N.; Jiang, J.-H.R.; Fages, F.; JIE-HONG JIANG | 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings | |||
51 | 2017 | Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits | Cheng-Yu Shih; Chun-Hong Shih; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | Design Automation Conference (DAC) | 0 | 0 | |
52 | 2017 | Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines | Chun-Hong Shih; Jie-Hong Roland Jiang; JIE-HONG JIANG ; 江介宏 | IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) | 0 | 0 | |
53 | 2017 | Logic Synthesis of Recombinase Based Genetic Circuits | Tai-Yin Chiu; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | Scientific Reports | 8 | 7 | |
54 | 2017 | Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation | Chun-Ning Lai; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | Design Automation Conference (DAC) | 2 | 0 | |
55 | 2017 | Solving Stochastic Boolean Satisfiability under Random-Exist Quantification | Nian-Ze Lee; Yen-Shi Wang; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | International Joint Conference on Artificial Intelligence (IJCAI) | 11 | 0 | |
56 | 2017 | RecombinaseBased Genetic Circuit Optimization | Chun-Ning Lai; Jie-Hong Jiang; Francois Fages; JIE-HONG JIANG | IEEE Biomedical Circuits and Systems Conference (BioCAS) | |||
57 | 2017 | Homing Sequence Derivation with Quantified Boolean Satisfiability | Hung-En Wang; Kuan-Hua Tu; Jie-Hong R. Jiang; Natalia Kushik; JIE-HONG JIANG ; 江介宏 | IFIP International Conference on Testing of Software and Systems (ICTSS) | 7 | 0 | |
58 | 2017 | A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning | Hsiao-Lei Chien; Mei-Yen Chiu; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | IEEE Transaction on CAD of Integrated Circuits and Systems | 0 | 0 | |
59 | 2017 | Sequential Engineering Change Order under Retiming and Resynthesis | Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | International Conference on Computer-Aided Design (ICCAD) | 5 | 0 | |
60 | 2017 | RecombinaseBased Genetic Circuit Optimization | Chun-Ning Lai; Jie-Hong Jiang; Francois Fages; JIE-HONG JIANG ; 江介宏 | IEEE Biomedical Circuits and Systems Conference (BioCAS) | |||
61 | 2016 | 2QBF: Challenges and Solutions | Valeriy Balabanov; Jie-Hong Rol; Jiang, Christoph Scholl; Alan Mishchenko; Robert K. Brayton; JIE-HONG JIANG | Int'l Conf. on Theory and Applications of Satisfiability Testing (SAT) | |||
62 | 2016 | String Analysis via Automata Manipulation with Logic Circuit Representation | Hung-En Wang; Tzung-Lin Tsai; Chun-Han Lin; Fang Yu; Jie-Hong R. Jiang; JIE-HONG JIANG | Int'l Conf. on Computer Aided Verification (CAV) | |||
63 | 2016 | Design Partitioning for Large Scale Equivalence Checking and Functional Correction | Grace Wu; Yi-Tin Sun; JIE-HONG JIANG | Design Automation Conference (DAC) | |||
64 | 2016 | Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification | Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 4 | |
65 | 2016 | Flexibility and Optimization of QBF Skolem-Herbrand Certificates | Valeriy Balabanov; Shuo-Ren Lin; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 0 | 0 | |
66 | 2016 | Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits | Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |
67 | 2016 | Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits | Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG ; 江介宏 | International Conference on Computer-Aided Design (ICCAD) | 5 | 0 | |
68 | 2016 | Clauses Versus Gates in CEGAR-Based 2QBF Solving. | Balabanov, Valeriy; Jiang, Jie-Hong Roland; Mishchenko, Alan; Scholl, Christoph; JIE-HONG JIANG | Beyond NP, Papers from the 2016 AAAI Workshop, Phoenix, Arizona, USA, February 12, 2016. | |||
69 | 2015 | Asynchronous QDI Circuit Synthesis from Signal Transition Protocols | Bo-Yuan Huang; Yi-Hsiang Lai; JIE-HONG JIANG | International Conference on Computer- Aided Design (ICCAD) | |||
70 | 2015 | SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis | Chun-Hong Shih; Yi-Hsiang Lai; JIE-HONG JIANG | International Conference on Computer- Aided Design (ICCAD) | |||
71 | 2015 | Property-directed synthesis of reactive systems from safety specifications | Ting-Wei Chiang; JIE-HONG JIANG | International Conference on Computer- Aided Design (ICCAD) | |||
72 | 2015 | Deriving Compositionally Deadlock-free Componenets over Synchronous Automata Compositions | Nina Yevtushenko; Khaled El-Fakih; Tiziano Villa; Jie-Hong R. Jiang; JIE-HONG JIANG | The Computer Journal | 0 | ||
73 | 2015 | A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines | Yi-Hsiang Lai; Chi-Chuan Chuang; JIE-HONG JIANG | International Conference on Computer- Aided Design (ICCAD) | |||
74 | 2015 | Synthesizing Configurable Biochemical Implementation of Linear Systems from Their Transfer Function Specifications | Tai-Yin Chiu; Hui-Ju K. Chiang; Ruei-Yang Huang; Jie-Hong R. Jiang; Francois Fages; JIE-HONG JIANG | PLOS ONE | 9 | ||
75 | 2015 | QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving | Kuan-Hua Tu; Tzu-Chen Hsu; JIE-HONG JIANG | International Conference on Theory and Applications of Satisfiability Testing (SAT) | |||
76 | 2015 | Reconfigurable neuromorphic computation in biochemical systems | Hui-Ju Katherine Chiang; Jie-Hong R. Jiang; Francois Fages; JIE-HONG JIANG | Int'l Conf. of the IEEE Engineering in Medicine and Biology Society (EMBC) | |||
77 | 2015 | Scalable Sequence-Constrained Retention Register Minimization in Power Gating Design | Ting-Wei Chiang; Kai-Hui Chang; Yen-Ting Liu; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC) | |||
78 | 2015 | Hybrid Simulations of Heterogeneous Biochemical Models in SBML | Hui-Ju Katherine Chiang; Francois Fages; Jie-Hong Roland Jiang; Sylvain Soliman; JIE-HONG JIANG | ACM Transactions on Modeling and Computer Simulation | 1 | ||
79 | 2015 | Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs | Valeriy Balabanov; Jie-Hong R. Jiang; Mikolas Janota; Magdalena Widl; JIE-HONG JIANG | AAAI Conference on Artificial Intelligence (AAAI-15) | |||
80 | 2014 | Towards Formal Evaluation and Verification of Probabilistic Design | Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG | International Conference on Computer- Aided Design (ICCAD) | 4 | 0 | |
81 | 2014 | Building Reconfigurable Circuitry in a Biochemical World | Hui-Ju Katherine Chiang; Jie-Hong Rol; Jiang; Franç ois Fages; JIE-HONG JIANG | IEEE Biomedical Circuits and Systems Conference (BioCAS) | 6 | 0 | |
82 | 2014 | QBF Resolution Systems and their Proof Complexities | Valeriy Balabanov; Magdalena Widl; Jie-Hong R. Jiang; JIE-HONG JIANG | International Conference on Theory and Applications of Satisfiability Testing (SAT) | 72 | 0 | |
83 | 2014 | Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification | Chi-Yuan Liu; Hui-Ju K. Chiang; Yao-Wen Chang; Jie-Hong R. Jiang; YAO-WEN CHANG ; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC) | 4 | 0 | |
84 | 2014 | Configurable Linear Control of Biochemical Systems | JIE-HONG JIANG | International Workshop on Bio-Design Automation (IWBDA) | |||
85 | 2014 | Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits | Chi-Chuan Chuang; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC) | 10 | 0 | |
86 | 2014 | Henkin quantifiers and Boolean formulae: A certification perspective of DQBF | Valeriy Balabanov; Hui-Ju K. Chiang; Jie-Hong R. Jiang; JIE-HONG JIANG | Theoretical Computer Science (TCS) | 32 | 27 | |
87 | 2014 | Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. | Chuang, Chi-Chuan; Lai, Yi-Hsiang; JIE-HONG JIANG | The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014 | |||
88 | 2013 | Software Workarounds for Hardware Errors: Instruction Patch Synthesis | Tsung-Po Liu; Shuo-Ren Lin; Jie-Hong R. Jiang; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) | 1 | 1 | |
89 | 2013 | Automatic Test Pattern Generation for Delay Defects Using Timed Characteristic Functions | Shin-Yann Ho; Shuo-Ren Lin; Ko-Lung Yuan; Chien-Yen Kuo; Kuan-Yu Liao; Jie-Hong R. Jiang; Chien-Mo James Li; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
90 | 2013 | Encoding Multi-Valued Functions for Symmetry | Ko-Lung Yuan; Chien-Yen Kuo; Jie-Hong R. Jiang; Meng-Yen Li; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
91 | 2013 | Synthesizing Multiple Boolean Functions Using Interpolation on a Single Proof | Georg Hofferek; Ashutosh Gupta; Bettina Konighofer; Jie-Hong Rol; Jiang, Roderick Bloem; JIE-HONG JIANG | International Conference on Formal Methods in Computer-Aided Design (FMCAD) | |||
92 | 2013 | On the Hybrid Composition and Simulation of Heterogeneous Biochemical Models | Hui-Ju Katherine Chiang; Francois Fages; Jie-Hong R. Jiang; Sylvain Soliman; JIE-HONG JIANG | International Conference on Computational Methods in Systems Biology (CMSB) | 1 | 0 | |
93 | 2013 | Functional Timing Analysis Made Fast and General | Yi-Ting Chung; Jie-Hong R. Jiang; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) | 9 | 7 | |
94 | 2013 | Species Minimization in Computation with Biochemical Reactions | Ruei-Yang Huang; De-An Huang; Hui-Ju Katherine Chiang; Jie-Hong R. Jiang; Francois Fages; JIE-HONG JIANG | International Workshop on Bio-Design Automation (IWBDA) | |||
95 | 2013 | Synthesis of feedback decoders for initialized encoders | Kuan-Hua Tu; Jie-Hong R. Jiang; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC) | 1 | 0 | |
96 | 2013 | Automatic test pattern generation for delay defects using timed characteristic functions. | Ho, Shin-Yann; Lin, Shuo-Ren; Yuan, Ko-Lung; Kuo, Chien-Yen; Liao, Kuan-Yu; Jiang, Jie-Hong R.; CHIEN-MO LI ; JIE-HONG JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | 2 | 0 | |
97 | 2013 | Encoding multi-valued functions for symmetry. | Yuan, Ko-Lung; Kuo, Chien-Yen; Jiang, Jie-Hong R.; Li, Meng-Yen; JIE-HONG JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | |||
98 | 2012 | Compiling Program Control Flows into Biochemical Reactions | De-An Huang; Jie-Hong R. Jiang; Ruei-Yang Huang; Chi-Yun Cheng; JIE-HONG JIANG | Int'l Conf. on Computer-Aided Design (ICCAD'12) | 9 | 0 | |
99 | 2012 | Automatic Decoder Synthesis: Methods and Case Studies | Hsiou-Yuan Liu; Yen-Cheng Chou; Chen-Hsuan Lin; Jie-Hong R. Jiang; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) | 2 | 2 | |
100 | 2012 | Unified QBF Certification and its Applications | Valeriy Balabanov; Jie-Hong R. Jiang; JIE-HONG JIANG | Formal Methods in System Design (FMSD) | 119 | 82 | |
101 | 2012 | When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way | Cheng-Shen Han; Jie-Hong R. Jiang; JIE-HONG JIANG | International Conference on Computer Aided Verification (CAV'12) | 26 | 0 | |
102 | 2012 | Improving Design Verifiability by Early RTL Coverability Analysis | Kai-Hui Chang; Chia-Wei Chang; Jie-Hong R. Jiang; Chien-Nan Jimmy Liu; JIE-HONG JIANG | ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12) | 0 | 0 | |
103 | 2012 | Henkin Quantifiers and Boolean Formulae | Valeriy Balabanov; Hui-Ju Katherine Chiang; Jie-Hong R. Jiang; JIE-HONG JIANG | Int'l Conference on the Theory and Applications of Satisfiability Test (SAT'12) | 3 | 0 | |
104 | 2012 | Functional Timing Analysis Made Fast and General | Yi-Ting Chung; Jie-Hong R. Jiang; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC'12) | 4 | 7 | |
105 | 2012 | Clock Rescheduling for Timing Engineering Change Orders | Kuan-Hsien Ho; Xin-Wei Shih; Jie-Hong R. Jiang; JIE-HONG JIANG | Asia and South Pacific Design Automation Conference (ASP-DAC'12) | 4 | 0 | |
106 | 2012 | TRECO: Dynamic technology remapping for timing engineering change orders | Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG ; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | 8 | |
107 | 2012 | Reducing test point overhead with don't-cares | Chang, K.-H.; Chang, C.-W.; Jiang, J.-H.R.; Liu, C.-N.J.; JIE-HONG JIANG | Midwest Symposium on Circuits and Systems | |||
108 | 2011 | Scalable Don't-Care-Based Logic Optimization and Resynthesis | Alan Mishchenko; Robert Brayton; Jie-Hong R. Jiang; Stephen Jang; JIE-HONG JIANG | ACM Transactions on Reconfigurable Technology and Systems (TRETS) | 50 | 47 | |
109 | 2011 | Towards Completely Automatic Decoder Synthesis | Hsiou-Yuan Liu; Yen-Cheng Chou; Chen-Hsuan Lin; Jie-Hong R. Jiang; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer Aided Design (ICCAD'11) | 5 | 0 | |
110 | 2011 | Resolution Proofs and Skolem Functions in QBF Evaluation and Applications | Valeriy Balabanov; Jie-Hong R. Jiang; JIE-HONG JIANG | Int'l Conf. on Computer Aided Verification (CAV'11) | 25 | 0 | |
111 | 2011 | Bi-decomposition Using SAT and Interpolation | Ruei-Rung Lee; Jie-Hong Rol Jiang; Wei-Lun Hung; JIE-HONG JIANG | ||||
112 | 2011 | Ashenhurst Decomposition Using SAT and Interpolation | Hsuan-Po Lin; Jie-Hong Rol Jiang; Ruei-Rung Lee; JIE-HONG JIANG ; Hsuan-Po Lin;Jie-Hong Rol Jiang;Ruei-Rung Lee | ||||
113 | 2011 | Extracting Functions from Boolean Relations Using SAT and Interpolation | Jie-Hong Rol; Jiang, Hsuan-Po Lin; Wei-Lun Hung; JIE-HONG JIANG | ||||
114 | 2011 | Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization | Chang, C.-W.; Chou, H.-Z.; Chang, K.-H.; Jiang, J.-H.R.; Liu, C.-N.J.; Hsiao, C.-H.; JIE-HONG JIANG ; SY-YEN KUO | Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011 | 3 | 0 | |
115 | 2011 | Bi-decomposition using SAT and interpolation | Lee, R.-R.; Jiang, J.-H.R.; Hung, W.-L.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | |||
116 | 2011 | Ashenhurst decomposition using SAT and interpolation | Lin, H.-P.; Jiang, J.-H.R.; Lee, R.-R.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | |||
117 | 2011 | Extracting functions from boolean relations using SAT and interpolation | Jiang, J.-H.R.; Lin, H.-P.; Hung, W.-L.; JIE-HONG JIANG | Advanced Techniques in Logic Synthesis, Optimizations and Applications | |||
118 | 2010 | Boolean Matching of Function Vectors with Strengthened Learning | Chih-Fan Lai; Jie-Hong R. Jiang; Kuo-Hua Wang; JIE-HONG JIANG | Int'l Conf. on Computer-Aided Design (ICCAD'10) | 9 | 0 | |
119 | 2010 | A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques | Bo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
120 | 2010 | BooM: A Decision Procedure for Boolean Matching with Abstraction and Dynamic Learning | Chih-Fan Lai; Jie-Hong R. Jiang; Kuo-Hua Wang; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC'10) | 13 | 0 | |
121 | 2010 | Hardware Equivalence and Property Verification | Jie-Hong R. Jiang; Tiziano Villa; JIE-HONG JIANG | ||||
122 | 2010 | To SAT or Not to SAT: Scalable Exploration of Functional Dependency | Jie-Hong R. Jiang; Chih-Chun Lee; Alan Mishchenko; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE Transactions on Computers (TCOMP) | |||
123 | 2010 | TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders | Kuan-Hsien Ho; Jie-Hong R. Jiang; Yao-Wen Chang; YAO-WEN CHANG ; JIE-HONG JIANG | Asia and South Pacific Design Automation Conference (ASP-DAC'10) | 14 | 9 | |
124 | 2010 | Hardware Equivalence and Property Verification. | Jiang, Jie-Hong Roland; Villa, Tiziano; Crama, Yves; Hammer, Peter L.; JIE-HONG JIANG | Boolean Models and Methods in Mathematics, Computer Science, and Engineering | |||
125 | 2009 | Interpolating Functions from Large Boolean Relations | Jie-Hong R. Jiang; Hsuan-Po Lin; Wei-Lun Hung; JIE-HONG JIANG | Int'l Conf. on Computer-Aided Design (ICCAD'09) | 38 | 0 | |
126 | 2009 | Symmetrization in Digital Circuit Optimization | Natalia Eliseeva; Jie-Hong R. Jiang; Natalia Kushik; Nina Yevtushenko; JIE-HONG JIANG | IEEE East-West Design & Test Symposium (EWDTS'09) | |||
127 | 2009 | Quantifier Elimination via Functional Composition | JIE-HONG JIANG | Int'l Conf. on Computer Aided Verification (CAV'09) | |||
128 | 2009 | Scalable Don't Care Based Logic Optimization and Resynthesis | Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Stephen Jang; JIE-HONG JIANG | ACM International Symposium on Field-Programmable Gate Arrays (FPGA'09) | 23 | 0 | |
129 | 2009 | Logic Synthesis in a Nutshell | Jie-Hong R. Jiang; Srinivas Devadas; JIE-HONG JIANG | ||||
130 | 2009 | Logic Synthesis in a Nutshell | Jiang, J.H.; Devadas, S.; JIE-HONG JIANG | Electronic Design Automation | |||
131 | 2008 | To SAT or Not to SAT: Ashenhurst Decomposition in a Large Scale | Hsuan-Po Lin; Jie-Hong R. Jiang; Ruei-Rung Lee; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'08) | 22 | 0 | |
132 | 2008 | A Dynamic Accuracy-Refinement Approach to Timing-Driven Technology Mapping | Sz-Cheng Huang; Jie-Hong R. Jiang; JIE-HONG JIANG | IEEE Int'l Conf. on Computer Design (ICCD'08) | 0 | 0 | |
133 | 2008 | 奈米IC設計之前瞻電子設計自動化技術-子計畫三:於奈米積體電路製程變異下考量實體設計之穩健邏輯合成研究 (新制多年期第1年) | 江介宏 | ||||
134 | 2008 | 系統驗證之可重用性研究(I) | 江介宏 | ||||
135 | 2008 | 自動機與有限狀態機方程解於數位電路最佳化之應用 (新制多年期第2年) | 江介宏 | ||||
136 | 2008 | Bi-Decomposing Large Boolean Functions via Interpolation and Satisfiability Solving | Ruei-Rung Lee; Jie-Hong R. Jiang; Wei-Lun Hung; JIE-HONG JIANG | ACM/IEEE Design Automation Conference (DAC'08) | 35 | 0 | |
137 | 2008 | Bi-decomposing large Boolean functions via interpolation and satisfiability solving. | Lee, Ruei-Rung; Jiang, Jie-Hong Roland; Hung, Wei-Lun; JIE-HONG JIANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | |||
138 | 2007 | Inductive Equivalence Checking under Retiming and Resynthesis | Jie-Hong R. Jiang; Wei-Lun Hung; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07) | 11 | 0 | |
139 | 2007 | Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving | Chih-Chun Lee; Jie-Hong R. Jiang; Chung-Yang Huang; Alan Mishchenko; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07) | |||
140 | 2007 | Quantum Mechanical Search and Harmonic Perturbation | Jie-Hong R. Jiang; Dah-Wei Chiou; Cheng-En Wu; JIE-HONG JIANG | Quantum Information Processing | 1 | 1 | |
141 | 2007 | A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits | Chin-Hsiung Hsu; Szu-Jui Chou; Jie-Hong R. Jiang; Yao-Wen Chang; JIE-HONG JIANG | Int'l Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS'07) | 0 | 0 | |
142 | 2007 | 自動機與有限狀態機方程解於數位電路最佳化之應用 (新制多年期第1年) | 江介宏 | ||||
143 | 2007 | Quantum Mechanical Search and Harmonic Perturbation | Jie-Hong R. Jiang; Dah-Wei Chiou; Cheng-En Wu; JIE-HONG JIANG | 1 | 1 | ||
144 | 2006 | Retiming and Resynthesis: A Complexity Perspective | Jie-Hong R. Jiang; Robert K. Brayton; JIE-HONG JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 24 | 13 | |
145 | 2005 | Applied Logic & Computation for System Design- An introductory invitation | Jiang, Jie-Hong R.; 江介宏 | ||||
146 | 2005 | On Some Transformation Invariants under Retiming and Resynthesis | JIE-HONG JIANG | Int'l Conf. on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'05) | |||
147 | 2005 | Efficient Solution of Language Equations Using Partitioned Representations | Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Tiziano Villa; Nina Yevtushenko; JIE-HONG JIANG | Design Automation and Test in Europe (DATE'05) | 7 | 0 | |
148 | 2004 | On Breakable Cyclic Definitions | Jie-Hong R. Jiang; Alan Mishchenko; Robert K. Brayton; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'04) | 7 | 0 | |
149 | 2004 | Functional Dependency for Verification Reduction | Jie-Hong R. Jiang; Robert K. Brayton; JIE-HONG JIANG | Int'l Conf. on Computer Aided Verification (CAV'04) | 18 | ||
150 | 2004 | Functional dependency for verification reduction | Jiang, J.-H.R.; Brayton, R.K.; JIE-HONG JIANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | |||
151 | 2004 | Functional Dependency for Verification Reduction. | Jiang, Jie-Hong Roland; Brayton, Robert K.; JIE-HONG JIANG | Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings | |||
152 | 2003 | On the Verification of Sequential Equivalence | JIE-HONG JIANG ; Robert K. Brayton | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 23 | 22 | |
153 | 2003 | Reducing Multi-Valued Algebraic Operations to Binary. | Jiang, Jie-Hong Roland; Mishchenko, Alan; Brayton, Robert K.; JIE-HONG JIANG | 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany | |||
154 | 2003 | Reducing multi-valued algebraic operations to binary | Jiang, J.-H.R.; Mischenko, A.; Brayton, R.K.; JIE-HONG JIANG | Proceedings -Design, Automation and Test in Europe, DATE | |||
155 | 2002 | Optimization of multi-valued multi-level networks | Gao, M.; Jiang, J.-H.; Jiang, Y.; Li, Y.; Mishchenko, A.; Sinha, S.; Villa, T.; Brayton, R.; JIE-HONG JIANG | Proceedings of The International Symposium on Multiple-Valued Logic | |||
156 | 2001 | Unified functional decomposition via encoding for FPGA technology mapping | Jiang, J.-H.; Jou, J.-Y.; Huang, J.-D.; JIE-HONG JIANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |||
157 | 1999 | Optimum loading dispersion for high-speed tree-type decision circuitry. | Jiang, Jie-Hong Roland; JIE-HONG JIANG ; HUI-RU JIANG | Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999 | 0 | 0 | |
158 | 1998 | Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. | Jiang, Jie-Hong Roland; Jou, Jing-Yang; Huang, Juinn-Dar; JIE-HONG JIANG | Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998. | |||
159 | 1997 | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. | Jiang, Jie-Hong R.; Jou, Jing-Yang; Huang, Juinn-Dar; Wei, Jung-Shian; JIE-HONG JIANG | Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997 |