公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1994 | Back gate bias dependent quasi-saturation in a high-voltage SOI MOSFET: 2D analysis and closed-form analytical model | Liu, C.M.; Kuo, J.B. | SOI Conference, 1994 Proceedings., 1994 IEEE International | 0 | 0 | |
1993 | A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI | Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB | IEEE International Symposium on Circuits and Systems, 1993. ISCAS '93 | 0 | 0 | |
1992 | BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI | Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB | Electronics Letters | | | |
1991 | BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network | Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB | Electronics Letters | | | |
1991 | A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for neural network VLSI operating at 77 K | Chou, T.L.; Wong, E.J.; Lee, W.C.; Kuo, J.B. | Custom Integrated Circuits Conference, 1991. | 0 | 0 | |
1991 | A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for pattern recognition neural network VLSI operating at 77 K | Chou, T.L.; Wong, E.J.; Kuo, J.B. | Circuits and Systems, 1991., IEEE International Sympoisum on | 0 | 0 | |
1991 | A BiCMOS tristate buffer for high-speed microprocessor VLSI | Kuo, J.B.; Liao, H.J.; KuoJB | Fourth Annual IEEE International ASIC Conference and Exhibit, 1991 | 0 | 0 | |
1995 | A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation | Liu, C.M.; Shone, F.C.; Kuo, J.B. | Power Semiconductor Devices and ICs, 1995. ISPSD '95. Proceedings of the 7th International Symposium on | 0 | 0 | |
1991 | A coded block adaptive neural network structure for pattern recognition VLSI | Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB | 1991 International Symposium on VLSI Technology, Systems, and Applications | 2 | 0 | |
1993 | A coded block neural network system suitable for VLSI implementation using an adaptive learning-rate epoch-based back propagation technique | Mao, M.W.; Chen, B.Y.; Kuo, J.B. | Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on | 0 | 0 | |
1997 | Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects | Kuo, J.B.; Su, K.W.; KuoJB | IEEE International SOI Conference | 0 | 0 | |
1992 | Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature | Kuo, J.B.; Sim, J.H.; KuoJB | Electronics Letters | | | |
1991 | Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program | Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB | Custom Integrated Circuits Conference, 1991 | 0 | 0 | |
1994 | Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI | Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB | Custom Integrated Circuits Conference, 1994 | 0 | 0 | |
1991 | Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator | Kuo, J.B.; Chen, Y.W.; KuoJB | Bipolar Circuits and Technology Meeting, 1991. | 0 | 0 | |
1995 | A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems | Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB | ASIC Conference and Exhibit, 1995. | 0 | 0 | |
1999 | A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique | Liu, S.C.; Kuo, J.B. | SOI Conference, 1999. Proceedings. 1999 IEEE International | 0 | 0 | |
2000 | A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique | Wang, Bo-Ting; Kuo, J.B. | Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on | 0 | 0 | |
2000 | A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability | Wang, B.T.; Kuo, J.B. | Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on | 7 | 0 | |
1991 | A one-transistor synapse circuit with an analog LMS adaptive feedback for neural network VLSI | Lu, T.C.; Chiang, M.L.; Kuo, J.B. | Circuits and Systems, 1991., IEEE International Sympoisum on | 0 | 0 | |