公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2012 | Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits | M.-L. Fan; Y.-N. Chen; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 39 | 34 | |
2017 | Analysis of subthreshold swing and internal voltage amplification for hysteresis-free negative capacitance FinFETs | Chiu P.-C; Hu V.P.-H.; VITA PI-HO HU | 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings | 5 | 0 | |
2018 | Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs | P.-C. Chiu; VITA PI-HO HU | Japanese Journal of Applied Physics | 1 | 2 | |
2011 | Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 4 | 4 | |
2012 | Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking | M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU | IEEE Electron Device Letters | 14 | 10 | |
2019 | Comparative Analysis of Negative Capacitance Junctionless and Inversion Mode Transistors for Low Power Applications | Gupta M; Hu V.P.-H.; VITA PI-HO HU | 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 | 0 | 0 | |
2013 | Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET | V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; VITA PI-HO HU ; V. P.-H. Hu; M.-L. Fan; P. Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Electron Devices | 22 | 20 | |
2011 | Comparison of 4T and 6T FinFET SRAM cells for subthreshold operation considering variability-A model-based approach | Fan M.-L; Wu Y.-S; VITA PI-HO HU ; Hsieh C.-Y; Su P; Chuang C.-T. | IEEE Transactions on Electron Devices | 34 | 22 | |
2021 | Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-term FeFET Retention Model | Mo F; Xiang J; Mei X; Sawabe Y; Saraya T; Hiramoto T; Su C.-J; VITA PI-HO HU ; Kobayashi M. | Digest of Technical Papers - Symposium on VLSI Technology | 4 | | |
2013 | Design and Analysis of Robust Tunneling FET SRAM | Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; P. Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Electron Devices | 36 | 30 | |
2019 | Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET | Lin H.-H; Hu V.P.-H.; VITA PI-HO HU | Proceedings - International Symposium on Quality Electronic Design, ISQED | 4 | 0 | |
2018 | Device Designs of III-V Tunnel FETs for Performance Enhancements through Line Tunneling | Wang C.-T; Hu V.P.-H.; VITA PI-HO HU | 2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings | 4 | 0 | |
2022 | Efficient Erase Operation by GIDL Current for 3D Structure FeFETs with Gate Stack Engineering and Compact Long-Term Retention Model | Mo F; Xiang J; Mei X; Sawabe Y; Saraya T; Hiramoto T; Su C.-J; VITA PI-HO HU ; Kobayashi M. | IEEE Journal of the Electron Devices Society | 3 | 3 | |
2022 | Energy-and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors | Lee, Ming; Huang, Zi Yuan; Fan, Shao Fu; Lu, Yu Cheng; VITA PI-HO HU | Technical Digest - International Electron Devices Meeting, IEDM | 0 | 0 | |
2020 | Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS<inf>2</inf>FETs for SoC Scaling | Su, C.-W.; Lee, Y.-W.; Ho, T.-Y.; Cheng, C.-C.; Chen, T.-C.; Hung, T.Y.-T.; Li, J.-F.; Chen, Y.-G.; Li, L.-J.; VITA PI-HO HU | IEEE Transactions on Electron Devices | 9 | 10 | |
2019 | Evaluation of analog circuit performance for ferroelectric SOI MOSFETs considering interface trap charges and gate length variations | Lu Y.-C; Hu V.P.-H.; VITA PI-HO HU | 2019 Silicon Nanoelectronics Workshop, SNW 2019 | 7 | 0 | |
2016 | Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications | C.-H. Yu; M.-L. Fan; K.-C. Yu; Pin Su; C.-T. Chuang; VITA PI-HO HU | IEEE Transactions on Electron Devices | 16 | 17 | |
2014 | Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells | VITA PI-HO HU ; Fan M.-L; Su P; Chuang C.-T. | Proceedings - IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2014 | Evaluation of Stabilit, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits | Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合 | IEEE Journal on Emerging and Selected Topics in Circuits and Systems | 46 | 38 | |
2014 | Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices | Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; VITA PI-HO HU ; Y.-N. Chen; M.-L. Fan; V. P.-H. Hu; Pin Su; C.-T. Chuang; 胡璧合 | IEEE Transactions on Circuits and Systems I: Regular Papers | 13 | 9 | |