第 1 到 159 筆結果,共 159 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2023 | Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis | Hsieh, Bing Han; Liu, Yun Sheng; CHIEN-MO LI ; Nigh, Chris; Chern, Mason; Bhargava, Gaurav | Proceedings - International Test Conference | |||
2 | 2023 | Diagnosis of Quantum Circuits in the NISQ Era | Li, Yu Min; Hsieh, Cheng Yun; Li, Yen Wei; CHIEN-MO LI | Proceedings of the IEEE VLSI Test Symposium | 0 | 0 | |
3 | 2023 | Vmin Prediction Using Nondestructive Stress Test | Chen, Chun; Liao, Jeng Yu; CHIEN-MO LI ; Chen, Harry H.; Fang, Eric Jia Wei | Proceedings of the IEEE VLSI Test Symposium | 1 | 0 | |
4 | 2023 | High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns | Liang, Zhe Jia; Wu, Yu Tsung; Yang, Yun Feng; CHIEN-MO LI ; Chang, Norman; Kumar, Akhilesh; Li, Ying Shiun | Proceedings - International Test Conference | |||
5 | 2023 | Small Sampling Overhead Error Mitigation for Quantum Circuits | Hsieh, Cheng Yun; Tsai, Hsin Ying; Lu, Yuan Hsiang; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
6 | 2022 | Automatic test configuration and pattern generation (ATCPG) for neuromorphic chips | Chiu, I. Wei; Chen, Xin Ping; Hu, Jennifer Shueh Inn; CHIEN-MO LI | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
7 | 2022 | Diagnosing Double Faulty Chains through Failing Bit Separation | Kuo, Cheng Sian; Hsieh, Bing Han; CHIEN-MO LI ; Nigh, Chris; Bhargava, Gaurav; Chern, Mason | Proceedings - International Test Conference | 0 | 0 | |
8 | 2022 | ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption | Lin, Wei Chen; Chen, Chun; Hsieh, Chao Ho; CHIEN-MO LI ; Fang, Eric Jia Wei; Hsueh, Sung S.Y. | Proceedings - International Test Conference | 1 | 0 | |
9 | 2022 | Low-IR-Drop Test Pattern Regeneration Using A Fast Predictor | Liu, Shi Tang; Chen, Jia Xian; Wu, Yu Tsung; Hsieh, Chao Ho; CHIEN-MO LI ; Chang, Norman; Li, Ying Shiun; Chuang, Wen Tze | Proceedings - International Symposium on Quality Electronic Design, ISQED | 0 | 0 | |
10 | 2021 | Fault Modeling and Testing of Spiking Neural Network Chips | Hsieh, Yi Zhan; Tseng, Hsiao Yin; Chiu, I. Wei; CHIEN-MO LI | Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 | 2 | 0 | |
11 | 2021 | Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits | Chen T.-C; Pai C.-C; Hsieh Y.-Z; Tseng H.-Y; Chien-Mo J; Liu T.-T; CHIEN-MO LI ; TSUNG-TE LIU ; Chiu I.-W | Journal of Electronic Testing: Theory and Applications (JETTA) | 0 | 0 | |
12 | 2021 | Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization | Wu M.-T; Kuo C.-S; Li J.C.-M; Nigh C; Bhargava G.; CHIEN-MO LI | Proceedings - International Test Conference | |||
13 | 2021 | Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning | Kuo Y.-T; Lin W.-C; Chen C; Hsieh C.-H; Li J.C.-M; Jia-Wei Fang E; Hsueh S.S.-Y.; CHIEN-MO LI | Proceedings - International Test Conference | |||
14 | 2021 | Chip Performance Prediction Using Machine Learning Techniques | Su M.-Y; Lin W.-C; Kuo Y.-T; Li C.-M; Fang E.J.-W; Hsueh S.S.-Y.; CHIEN-MO LI | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | |||
15 | 2020 | Student engagement in the co-designing and co-teaching a cornerstone eecs design and implementation course at national Taiwan university | Lee, Jennifer Wen-Shya et al.; Lin, Kun-You ; Chen, Ho-Lin ; Chen, J.-P.; SHIH-YUAN CHEN ; CHIEN-MO LI ; Xu, R.-F.; TZI-DAR CHIUEH ; HSIAO-WEN CHUNG ; Chen, N.; SHI-CHUNG CHANG | International Conference on Higher Education Advances | 0 | 0 | |
16 | 2020 | Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips | Liu C.-Y; Wu M.-T; Li J.C.-M; Bhargava G; Nigh C.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | |||
17 | 2020 | High Efficiency and Low Overkill Testing for Probabilistic Circuits | Lee M.-T; Wu C.-H; Liu S.-T; Hsieh C.-Y; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | |||
18 | 2020 | Diagnosis technique for Clustered Multiple Transition Delay Faults | You Y.-S; Liu C.-Y; Wu M.-T; Chen P.-W; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | |||
19 | 2020 | Automatic IR-Drop ECO Using Machine Learning | Lin H.-Y; Fang Y.-C; Liu S.-T; Chen J.-X; Li C.-M; Fang E.J.-W.; CHIEN-MO LI | Proceedings - 2020 IEEE International Test Conference in Asia, ITC-Asia 2020 | |||
20 | 2019 | Test methodology for PCHB/PCFB Asynchronous Circuits | Shen, T.-Y.; Pai, C.-C.; Chen, T.-C.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - International Test Conference | 1 | 0 | |
21 | 2019 | DR-scan: Dual-rail Asynchronous Scan DfT and ATPG | Shih-An Hsieh; Ying-Hsu Wang; Ting-Yu Shen; Kuan-Yen Huang; Chia-Cheng Pai Tsai-Chieh Chen; James Chien-Mo Li; CHIEN-MO LI | IEEE Transactions on Computer Aided Design | 3 | 2 | |
22 | 2019 | ATPG and test compression for probabilistic circuits | Yang, K.-C.; Lee, M.-T.; Wu, C.-H.; CHIEN-MO LI | 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 | |||
23 | 2018 | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction | Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W. ; Li, J.C.M.; Jiang, J.-H.R.; JIE-HONG JIANG ; CHIEN-MO LI | Design Automation Conference | 5 | 0 | |
24 | 2018 | Test pattern compression for probabilistic circuits | Chang, C.-M.; Yang, K.-J.; Li, J.C.-M.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 0 | 0 | |
25 | 2018 | Parallel order ATPG for test compaction | Chen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | |||
26 | 2018 | Machine-learning-based dynamic IR drop prediction for ECO | Fang, Y.-C.; Lin, H.-Y.; Su, M.-Y.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
27 | 2018 | Diagnosis and repair of cells (DRC) responsible for power-supply-noise violations | Li, Y.-C.; Lin, S.-Y.; Lin, H.-Y.; CHIEN-MO LI | 2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018 | |||
28 | 2018 | IR drop prediction of ECO-revised circuits using machine learning | Lin, S.-Y.; Fang, Y.-C.; Li, Y.-C.; Liu, Y.-C.; Yang, T.-S.; Lin, S.-C.; Li, C.-M.; Fang, E.J.-W.; CHIEN-MO LI | Proceedings of the IEEE VLSI Test Symposium | |||
29 | 2018 | A new method for parameter estimation of high-order polynomial-phase signals. | Cao, Runqing; Li, James Chien-Mo; Zuo, Lei; Wang, Zeyu; Lu, Yunlong; CHIEN-MO LI | Signal Processing | |||
30 | 2017 | Physical-aware diagnosis of multiple interconnect defects | Chen, P.-H.; Lee, C.-L.; Chen, J.-Y.; Chen, P.-W.; CHIEN-MO LI | ITC-Asia 2017 - International Test Conference in Asia | 2 | 0 | |
31 | 2017 | PSN-aware Circuit Test Timing Prediction using Machine Learning | B. Liu; J. C.M. Li; CHIEN-MO LI | IET Computers & Digital Techniques | 9 | 6 | |
32 | 2017 | Automatic test pattern generation | Cheng, K.-T.T.; Wang, L.-C.; Li, H.; CHIEN-MO LI | Electronic Design Automation for IC System Design, Verification, and Testing | |||
33 | 2017 | Test Methodology for Dual-rail Asynchronous Circuits | Huang, K.-Y.; Shen, T.-Y.; CHIEN-MO LI | Proceedings - Design Automation Conference | |||
34 | 2017 | Robust test pattern generation for hold-time faults in nanometer technologies | Ho, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; CHIEN-MO LI | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | |||
35 | 2016 | A multicircuit simulator based on inverse jacobian matrix reuse | Lee, H.-I.; Han, C.-Y.; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
36 | 2016 | Test Pattern Modification for Average IR-Drop Reduction | Ding, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | |||
37 | 2016 | Power-supply-noise-aware timing analysis and test pattern regeneration | Han, C.-Y.; Li, Y.-C.; Kan, H.-T.; CHIEN-MO LI | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | |||
38 | 2015 | TARGET: Timing-AwaRe Gate Exhaustive Transition ATPG for Cell-internal Defects | A.F. Lin; Kuan-Yu Liao; Kuan-Ying Chiang; CHIEN-MO LI | IEEE VLSI/DAT | |||
39 | 2015 | DR Scan: DR-scan: A Test Methodology for Dual-rail Asynchronous Circuit | Shih-An. Hsieh; Y.-H.Wang; K.Y. Huang; CHIEN-MO LI | Design Automation Conference | |||
40 | 2015 | Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits | Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 9 | 0 | |
41 | 2015 | The Multimedia Piers-Harris Children's Self-Concept Scale 2: Its Psychometric Properties, Equivalence with the Paper-and-Pencil Version, and Respondent Preferences | Flahive, Mon-hsin Wang; Chuang, Ying-Chih; CHIEN-MO LI | Plos One | |||
42 | 2014 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | E. H. Ma; W. E. Wei; H. Y. Li; J. C. M. Li; I. C. Cheng; Y. H. Yeh; I-CHUN CHENG ; CHIEN-MO LI | IEEE Journal of Display Technology | 3 | 3 | |
43 | 2014 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk | CHIEN-MO LI ; M. H. Tsai; W. S. Ding; H. Y. Hsieh; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 3 | ||
44 | 2014 | Physical-aware Systematic Multiple Defect Diagnosis | CHIEN-MO LI ; P. J. Chen; C. C. Che; J. C. M. Li; S. F. Kuo; P. Y. Hsueh; C. Y. Kuo; J. N. Lee; CHIEN-MO LI | IET Proceedings Computers and Digital Techniques | 10 | ||
45 | 2014 | Divide and Conquer Diagnosis for Multiple Defects | CHIEN-MO LI ; SM Chao; PJ Chen; CHIEN-MO LI | IEEE International Test Conference | |||
46 | 2014 | Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D IC | CHIEN-MO LI ; H.Y. Hsieh; CHIEN-MO LI | IEEE 3D IC Test Workshop | |||
47 | 2014 | Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics | CHIEN-MO LI ; Y. L. Chen; W. R. Wu; C. N. J. Liu; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 16 | ||
48 | 2014 | Detect RRAM Defects in The Early Stage During Rnv8T Nonvolatile SRAM Testing | CHIEN-MO LI ; B.C. Bai; C.A. Chen; CHIEN-MO LI | IEEE International Test Conference | |||
49 | 2014 | GPU-Based Timing-Aware Test Generation for Small Delay Defects | CHIEN-MO LI ; K.Y. Liao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | IEEE European Test Symposium | |||
50 | 2014 | GALAXY: A Multi-Circuit Simulator based on Inverse Jacobian Matrix Reuse | CHIEN-MO LI ; H.Y. Lee; C.Y. Han; CHIEN-MO LI | IEEE/ACM Design Automation Conference | |||
51 | 2014 | A Flexible TFT Circuit Yield Optimizer Considering Process Variation, Aging, and Bending Effects | Wen-En Wei; Hung-Yi Li; Cheng-Yu Han; James Chien-Mo Li; Jian-Jang Huang; I-Chun Cheng; Chien-Nan Liu; Yung-Hui Yeh; I-CHUN CHENG ; JIAN-JANG HUANG ; CHIEN-MO LI | Journal of Display Technology | 5 | 2 | |
52 | 2014 | Testing of TSV-induced small delay faults for 3-D integrated circuits | Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James C.-M. Li; Krishnendu Chakrabarty; YI-CHANG LU ; CHIEN-MO LI | IEEE Trans. Very Large Scale Integration (VLSI) Systems | 17 | 13 | |
53 | 2014 | GPU-based timing-aware test generation for small delay defects. | Liao, Kuan-Yu; Chen, Po-Juei; Lin, Ang-Feng; Li, James Chien-Mo; Hsiao, Michael S.; Wang, Laung-Terng; CHIEN-MO LI | 19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014 | |||
54 | 2013 | Compact Test Pattern Selection for Small Delay Defect | CHIEN-MO LI ; J. Y. Chang; K. Y. Liao; S. C. Hsu; J. C. M. Li; J. C. Rau; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 18 | ||
55 | 2013 | Fault Simulation and Test Pattern Selection for Small Delay Defect Using GPU | CHIEN-MO LI ; SC Hsu; KY Liao; CHIEN-MO LI | VLSI/CAD | |||
56 | 2013 | Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM | CHIEN-MO LI ; BC Bai; C-L Hsu; MH Wu; CA Chen; YW Chen; KL Luo; LC Cheng; CHIEN-MO LI | IEEE Asian Test Symposium | |||
57 | 2013 | Defect Analysis and Fault Modeling for Rnv8T Nonvolatile SRAM | CHIEN-MO LI ; Bing-Chuan Bai; Chen-An Chen; Yee-Wen Chen; Ming-Hsueh Wu; Kun-Lun Luo; Chun-Lung Hsu; Liang-Chia Cheng; CHIEN-MO LI | IEEE Int’l Test Conf. | |||
58 | 2013 | Test Clock Domain Optimization to Avoid Scan Shift Failures due to Flip-flop Simultaneous Triggering | CHIEN-MO LI ; Y. C. Huang; M. H. Tsai; W. S. Ding; J. C. M. Li; M. T. Chang; M. H. Tsai; C. M. Tseng; H. C. Li; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
59 | 2013 | Test Generation of Path Delay Faults Induced by Defects in Power TSV | CHIEN-MO LI ; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI | IEEE Asian Test Symposium | |||
60 | 2013 | Test Pattern Modification for Average IR-drop Reduction | CHIEN-MO LI ; WS Ding; HY Hsieh; CHIEN-MO LI | IEEE Int’l Test Conf. | |||
61 | 2013 | Testing Leakage Faults of Power TSV in 3D IC | CHIEN-MO LI ; Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; K. Chakrabarty; CHIEN-MO LI | IEEE Int’l workshop on 3D IC | |||
62 | 2013 | Test generation of path delay faults induced by defects in power TSV | Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 2 | 0 | |
63 | 2013 | Automatic test pattern generation for delay defects using timed characteristic functions. | Ho, Shin-Yann; Lin, Shuo-Ren; Yuan, Ko-Lung; Kuo, Chien-Yen; Liao, Kuan-Yu; Jiang, Jie-Hong R.; CHIEN-MO LI ; JIE-HONG JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | 2 | 0 | |
64 | 2012 | Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis | CHIEN-MO LI ; W.L. Tsai; CHIEN-MO LI | IEEE Transactions on Computers | 9 | ||
65 | 2012 | Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC | CHIEN-MO LI ; C. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI | Active and Passive Electronic Components | |||
66 | 2012 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk | CHIEN-MO LI ; MH Tsai; WS Ting; CHIEN-MO LI | VTTW | |||
67 | 2012 | Systematic Open Via Diagnosis Based on Physical Features | CHIEN-MO LI ; P. J. Chen; C. C. Che; J. C. M. Li; K. Y. Tsai; S. F. Kuo; P. Y. Hsueh; Y. Y. Chen; J. N. Lee; CHIEN-MO LI | IEEE Silicon Debug and Diagnosis Workshop | |||
68 | 2012 | Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits, | CHIEN-MO LI ; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI | IEEE 3D IC Test workshop | |||
69 | 2012 | GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG, | CHIEN-MO LI ; K. Y. Liao; S. C. Hsu; CHIEN-MO LI | Design Automation Conference | |||
70 | 2012 | 3D IC test scheduling using simulated annealing | CHIEN-MO LI ; CY Hsu; CY Kuo; JCM Li; K. Chakrbarty; CHIEN-MO LI | IEEE VLSI-DAT | |||
71 | 2012 | A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores | CHIEN-MO LI ; G.M. Chiu; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 49 | ||
72 | 2012 | Flexible TFT Circuit Analyzer Considering Process Variation, Aging, and Bending Effects | CHIEN-MO LI ; EH Ma; WE Wei; CHIEN-MO LI | VLSI/CAD | |||
73 | 2012 | Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains, | CHIEN-MO LI ; JIUN-LANG HUANG ; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI ; JIUN-LANG HUANG | ACM Transactions on Design Automation of Electronic Systems (TODAES) | 0 | ||
74 | 2012 | Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs | CHIEN-MO LI ; B. C. Bai; CHIEN-MO LI | ITC | |||
75 | 2012 | Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk, | CHIEN-MO LI ; M. H. Tsai; W. S. Ting; CHIEN-MO LI | ITC | |||
76 | 2012 | GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG | CHIEN-MO LI ; KY Liao; SC Hsu; CHIEN-MO LI | IEEE Int’l Test Conf. | |||
77 | 2012 | An at-speed test technique for high-speed high-order adder by a 6.4-GHz 64-bit domino adder example | Wang, Y.-S.; Hsieh, M.-H.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | IEEE Transactions on Circuits and Systems I: Regular Papers | 3 | 3 | |
78 | 2011 | A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives | CHIEN-MO LI ; Liao, Kuan-Yu; Chang, Chia-Yuan; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
79 | 2011 | Thermal-aware Test scheduling for 3D ICs | CHIEN-MO LI ; CY Hsu; JCM Li; K. Chakrbarty; CHIEN-MO LI | IEEE Int’l 3D IC Test Workshop | |||
80 | 2011 | Compact test pattern Selection for Small Delay Defects | CHIEN-MO LI ; CY Chang; K.Y, Liao; CHIEN-MO LI | VLSI/CAD | |||
81 | 2011 | An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology | CHIEN-MO LI ; C. H. Cheng; CHIEN-MO LI | Journal of Electronic Testing | 8 | ||
82 | 2011 | Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan | CHIEN-MO LI ; R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI | International Test Conference | |||
83 | 2011 | Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips | CHIEN-MO LI ; W.C. Wang; CHIEN-MO LI | IET Computers & Digital Techniques | 2 | ||
84 | 2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |
85 | 2011 | Placement optimization of flexible TFT digital circuits | Liu, C.; Ma, E.-H.; Wei, W.-E.; Li, J.; Cheng, I.-C.; Yeh, Y.-H.; I-CHUN CHENG ; CHIEN-MO LI | IEEE Design and Test of Computers | 4 | 4 | |
86 | 2011 | An at-speed self-testable technique for the high speed domino adder | Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; CHIEN-MO LI ; CHUNG-PING CHEN | Proceedings of the Custom Integrated Circuits Conference | 1 | 0 | |
87 | 2011 | Placement optimization of flexible TFT digital circuits | Liu, W.-H.; Ma, E.-H.; Wei, W.-E.; CHIEN-MO LI | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | |||
88 | 2011 | Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese Children | Flahive, Mon-hsin Wang; Chuang, Ying-Chih; CHIEN-MO LI | Journal of Psychoeducational Assessment | |||
89 | 2010 | Static timing analysis for flexible TFT circuits | CHIEN-MO LI ; Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; CHIEN-MO LI | Design Automation Conference (DAC) | |||
90 | 2010 | CSER: BISER-based concurrent soft-error resilience | CHIEN-MO LI ; JIUN-LANG HUANG ; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | |||
91 | 2010 | DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in | CHIEN-MO LI ; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 1 | ||
92 | 2010 | Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium | CHIEN-MO LI ; J. Y. Wen; CHIEN-MO LI | ||||
93 | 2010 | Row-LFSR-Column (RLC) Test Response Masking Technique | CHIEN-MO LI ; WC Wang; CHIEN-MO LI | VLSI/CAD | |||
94 | 2010 | Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> Testing | Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI | IEEE/OSA Journal of Display Technology | 2 | 1 | |
95 | 2009 | Time-space test response compaction and diagnosis based on BCH codes | CHIEN-MO LI ; F. M. Wang; W.-C. Wang; CHIEN-MO LI | IET Computers & Digital Techniques | 0 | ||
96 | 2009 | Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits | Shiue-Tsung Shen,; Wei-Hsiao Liu,; En-Hua Ma,; J. C.-M. Li,; I-Chun Cheng,; I-CHUN CHENG ; CHIEN-MO LI | IEEE Asian Test Symposium | 0 | 0 | |
97 | 2009 | 包含未知訊號之測試結果壓縮設計 | 王偉哲 李建模; CHIEN-MO LI | ||||
98 | 2009 | Electronic Design Automation | CHIEN-MO LI ; J. C.-M. Li; M. Hsiao; CHIEN-MO LI | ||||
99 | 2009 | Power Scan: DFT for Power Switches in VLSI Designs | CHIEN-MO LI | International Test Conference | |||
100 | 2009 | Test Response Compaction in the Presence of Many Unknowns | CHIEN-MO LI ; Wei-Che Wang; James C.-M. Lim; Yi-Chih Sung; Amy Rao; Laung-Terng Wang; CHIEN-MO LI | VTTW | |||
101 | 2009 | Transition Fault Diagnosis Using At-speed Test Patterns | CHIEN-MO LI ; Shang-Feng Chao; Jheng-Yang Ciou; CHIEN-MO LI | IEEE Int’l Workshop on RTL and High Level Testing | |||
102 | 2009 | Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs | CHIEN-MO LI ; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI | Asia and South Pacific Design Automation Conference, ASP-DAC | |||
103 | 2009 | Bridging Fault Diagnosis to Identify the Layer of Systematic Defects | CHIEN-MO LI ; B. R. Chen; CHIEN-MO LI | Asian Test Symposium | |||
104 | 2009 | Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits. | Shen, Shiue-Tsung; Liu, Wei-Hsiao; Ma, En-Hua; Li, James Chien-Mo; I-CHUN CHENG ; CHIEN-MO LI | Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan | 1 | 0 | |
105 | 2009 | Power scan: OFT for power switches in VLSI designs | Bai, B.-C.; Li, C.-M.; Kifli, A.; Tsai, E.; CHIEN-MO LI | Proceedings - International Test Conference | 0 | 0 | |
106 | 2009 | BIST design optimization for large-scale embedded memory cores. | Chien, Tzuo-Fan; Chao, Wen-Chi; Li, James Chien-Mo; Chang, Yao-Wen; Liao, Kuan-Yu; Chang, Ming-Tung; Tsai, Min-Hsiu; CHIEN-MO LI ; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 7 | 0 | |
107 | 2009 | Fault Simulation and Test Generation | Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI | Electronic Design Automation | |||
108 | 2008 | 非同步電路可測試設計 | 鄭啟玄; 李建模 | ||||
109 | 2008 | 可應用於軟性電子的TFT電路設計技術之開發-子計畫六:可應用於軟性電子數位電路測試及容錯技術之開發(2/3) | 李建模 | ||||
110 | 2008 | Simultaneous capture and shift power reduction test pattern generator for scan testing | CHIEN-MO LI ; H.T. Lin; CHIEN-MO LI | IET Computers & Digital Techniques | |||
111 | 2008 | Survey of Scan Chain Diagnosis | CHIEN-MO LI ; Y. Huang; R Guo; W.T. Cheng; CHIEN-MO LI | IEEE Design & Test of Computers | |||
112 | 2008 | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise, | CHIEN-MO LI ; Hsiu-Ting Lin; Jen-Yang Wen; James Li; Ming-Tung Chang; Min-Hsiu Tsai; Sheng-Chih Huang; Chih-Mou Tseng; CHIEN-MO LI | Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise | |||
113 | 2008 | IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores | CHIEN-MO LI ; Geng-Ming Chiu; C.-Y. Chiu; R-Y. Wen; CHIEN-MO LI | International Test Conference | |||
114 | 2008 | Diagnosis of Logic-chain Bridging Faults | CHIEN-MO LI ; Wei-Chih Liu; Wei-Lin Tsai; Hsiu-Ting Lin; CHIEN-MO LI | IEEE Int’l Workshop on RTL and High Level Testing | |||
115 | 2008 | An Asynchronous DFT Technique for TFT Macroelectronics | CHIEN-MO LI ; C. H. Cheng; C.-H. Hsu; CHIEN-MO LI | International Symposium on Flexible Electronics and Display (ISFED) | |||
116 | 2008 | Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture Clocks | CHIEN-MO LI ; Shang-Feng Chao; CHIEN-MO LI | VLSI/CAD | |||
117 | 2008 | Diagnosis of Multiple Scan Chain Timing Faults | CHIEN-MO LI ; W.S. Chuang; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 8 | ||
118 | 2008 | A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT Technology | CHIEN-MO LI ; C. H. Cheng; CHIEN-MO LI | VLSI/CAD | |||
119 | 2008 | Effective and Economic Phase Noise Testing for Single-Chip TV Tuners | CHIEN-MO LI ; J. C.-M. Li; P.-C. Lin; P.-C. Chiang; C.-M. Pan; C.W. Tseng; CHIEN-MO LI | IEEE Transactions on Instrumentation and Measurement | 0 | ||
120 | 2008 | Phase Noise Testing of Single Chip TV Tuners, | CHIEN-MO LI ; P.-C. Lin; C.-H. Hsu; J. C.-M. Li; C.-M. Chiang; C.-J. Pan,; CHIEN-MO LI | IEEE VLSI-DAT | |||
121 | 2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
122 | 2008 | A two-level simultaneous test data and time reduction technique for SOC | Liaw, Y.-T.; Bai, B.-C.; CHIEN-MO LI | Journal of Information Science and Engineering | |||
123 | 2007 | 可應用於軟性電子的TFT電路設計技術之開發-子計畫六:可應用於軟性電子數位電路測試及容錯技術之開發(1/3) | 李建模 | ||||
124 | 2007 | Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing | CHIEN-MO LI ; Chun-Yi Lee; CHIEN-MO LI | Journal of Low Power Electronic | |||
125 | 2007 | 適用於建築結構監控之無線感測網路系統-子計畫二:超低功率可容錯及自測基頻通訊積體電路之研製(I) | 李建模 | ||||
126 | 2007 | 奈米IC設計之前瞻電子設計自動化技術-子計畫六:在奈米製程下考量信號完整度之測試與診斷技術 (新制多年期第1年) | 李建模 | ||||
127 | 2007 | Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis | CHIEN-MO LI ; J. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI | IEEE Transactions on Computers | |||
128 | 2007 | Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique | CHIEN-MO LI ; B.-H. Chen; Wei-Chuang Kao; Bin-Chuan Bai; Shyue-Tsong Shen; CHIEN-MO LI | IEEE Asian Test Symposium | |||
129 | 2007 | Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies | CHIEN-MO LI ; C.Y. Lee; H.M. Lin; F.M. Wang; CHIEN-MO LI | IEEE Asian South Pacific Design Automation Conference (ASP-DAC) | |||
130 | 2006 | 跳躍式掃描: 低功率可測試設計 | CHIEN-MO LI ; 邱銘豪; 李建模 | ||||
131 | 2006 | Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique | CHIEN-MO LI ; Y. L Kao; W. S. Chuang; CHIEN-MO LI | IEEE International Test Conference | |||
132 | 2006 | VLSI Test Principles and Architectures | Laung-Terng Wang; Cheng-Wen Wu; Xiaoqing Wen; Khader S. Abdel-Hafez; Wen-Ben Jone; Rohit Kapur; Brion Keller; Kuen-Jong Lee; CHIEN-MO LI ; Mike Peng Li; Xiaowei Li; T.M. Mak; Yinghua Min; Benoit Nadeau-Dostie; Soumendu Bhattacharya; Mehrdad Nourani; Janusz Rajski; Charles Stroud; Erik H. Volkerink; Duncan M. (Hank) Walker; Shianling Wu; Nur A. Touba; Abhijit Chatterjee; Xinghao Chen; Kwang-Ting (Tim) Cheng; William Eklow; Michael S. Hsiao; Jiun-Lang Huang; Shi-Yu Huang | ||||
133 | 2006 | CRC BIST: A Low Peak Power Self Technique | CHIEN-MO LI ; Bo-Hua Chen; CHIEN-MO LI | VLSI/CAD | |||
134 | 2006 | Logic and fault simulation | Huang, J.-L. ; Li, J.C.-M. ; Walker, D.M. | VLSI Test Principles and Architectures | 0 | 0 | |
135 | 2005 | Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC | CHIEN-MO LI ; Li, J. C.-M.; E. J. McCluskey; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 26 | ||
136 | 2005 | Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains | CHIEN-MO LI | IEEE Transactions on Computers | 31 | ||
137 | 2005 | 掃描鏈中多重時間錯誤之診斷 | 李建模 | ||||
138 | 2005 | Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains | CHIEN-MO LI ; H.M. Lin; CHIEN-MO LI | International Test Conference | |||
139 | 2005 | 子計畫五:具有自我測試功能之低功率基頻數位收發機電路 設計(1/2) | 李建模 | ||||
140 | 2005 | Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains | CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 38 | ||
141 | 2005 | Jump Scan: A DFT Technique for Low Power Testing, | CHIEN-MO LI ; M.H. Chiu; CHIEN-MO LI | IEEE VLSI Test Symposium | |||
142 | 2005 | Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns | CHIEN-MO LI | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 5 | ||
143 | 2005 | Effective and Economic Phase Noise Testing for Single Chip TV Tuners | CHIEN-MO LI ; P.C. Lin; J. C.-M. Li; Chih-Ming Chiang; Chuo-Jan Pan; CHIEN-MO LI | VLSI/CAD Symposium | |||
144 | 2005 | A Two-level Test Data Compression and Test Time Reduction Technique for SOC | CHIEN-MO LI ; Yu-Te Liaw; CHIEN-MO LI | VLSI/CAD Symposium | |||
145 | 2005 | Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing | CHIEN-MO LI ; Lee, C-Y; CHIEN-MO LI | Asia Solid-State Circuit Conference (ASSCC) | |||
146 | 2004 | 單晶片電視調諧器之經濟有效測試方法 | 李建模 | ||||
147 | 2004 | A Design for Testability Technique for Low Power Delay Fault Testing | CHIEN-MO LI | IEICE Transactions on Electronics | |||
148 | 2004 | Diagnosis of Scan Chains with Multiple Timing Faults Using Single Excitation Patterns | CHIEN-MO LI ; C. K. Yo; CHIEN-MO LI | VLSI/CAD Symposium | |||
149 | 2004 | Design and Implementation of a Low Power Delay Fault Built-in Self Test Technique | CHIEN-MO LI ; L. W. Ko; CHIEN-MO LI | VLSI/CAD Symposium | |||
150 | 2004 | ELF-Murphy Data on Defects and Test Sets | CHIEN-MO LI ; E. J. McCluskey; A. Alyamani; J. C. M. Li; C. W. Tseng; E. Volkerink; F. F. Feriani; E. Li; S. Mitra; CHIEN-MO LI | IEEE VLSI Test Symposium | |||
151 | 2004 | 具有內建自我測試功能之5GHz超低功率無線通訊系統之研製─子計畫五:具有自我測試功能之低功率基頻數位收發機電路設計 | 李建模 | ||||
152 | 2002 | Experimental Results for Slow Speed Testing | CHIEN-MO LI ; C.W.Tseng; J.C.M. Li; E. J. McCluskey; CHIEN-MO LI | IEEE VLSI Test Symposium | |||
153 | 2002 | Diagnosis for Sequence Dependent Chips | CHIEN-MO LI ; Li, J. C.M.; E. J. McCluskey; CHIEN-MO LI | IEEE VLSI Test Symposium | |||
154 | 2001 | Testing for Resistive and Stuck Opens | CHIEN-MO LI ; Li, J. C.M.; Tseng, C.W.; E.J. McCluskey; CHIEN-MO LI | International Test Conference | |||
155 | 2001 | Diagnosis of Tunneling Opens | CHIEN-MO LI ; Li, J. C.M.; E.J. McCluskey; CHIEN-MO LI | IEEE VLSI Test Symposium | |||
156 | 2001 | Pseudo Random Testing Theoretical Models vs. Real Data | CHIEN-MO LI ; Mitra; S.; C.W. Tseng; J. C. M Li; E. J. McCluskey; CHIEN-MO LI | IEEE International Workshop on Test Resource Partitioning | |||
157 | 2000 | Testing for tunneling opens. | Li, Chien-Mo James; McCluskey, Edward J.; CHIEN-MO LI | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | |||
158 | 1998 | Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. | Chang, Jonathan T.-Y.; Tseng, Chao-Wen; Li, Chien-Mo James; Purtell, Mike; McCluskey, Edward J.; CHIEN-MO LI | Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998 | |||
159 | 1998 | IDDQ data analysis using current signature | Li, J.C.M.; McCluskey, E.J.; CHIEN-MO LI | Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 |